Using partitioning to help convergence in the standard-cell design automation methodology

Kapadia, H.; Horowitz, Mark

doi:10.1145/309847.310005

Cited by 6 publications

(1 citation statement)

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“…Another use of Vex in our research is in the area of improving the convergence of timing in the synthesis and placement loop [6]. During synthesis, it is necessary to make assumptions about the eventual placement of cells and hence length of wires (which are not known yet) when doing technology mapping.…”

Section: Current Toolsmentioning

confidence: 99%

Vex—A CAD toolbox

Bergmann

Horowitz

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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The increasing size and complexity of designs is making the use of hardware description languages (HDLs), such as Verilog and VHDL, more prevalent. They are able to describe both the initial design and intermediate representations of the design as it is readied for fabrication. For large designs, there inevitably are problems with the tool flow that require custom tools to be created. These tools must be able to access and modify the HDL for the design, requirements that often dwarf the tools' actual functionality, making them difficult to create without a large effort or cutting corners. During the FLASH project at Stanford we created Vex --a toolbox of components for dealing with Verilog, tied together with an interactive scripting language --that simplifies the creation of these tools. It was used to create a number of tools that were critical to our design's tape-out and has also been useful in creating design exploration and research tools.

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Section: Current Toolsmentioning

confidence: 99%