Using PDM on Multiport Memory Allocationin Data Path

Abstract

A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.

A graph-theoretic approach for register file based synthesis

“…In this section, we compare our results with the benchmark problems from Chen [4], Ahmad & Chen [1], and Kim k, Liu [6] and show that in every case SOUPS shows substantial improvements.…”

“…We generated a Force-Directed Schedule (see Figure 3) for the filter and derived an allocation as well as the RTL equations from this schedule. The register transfer level equations are given in [4]. The architecture evolved by SOUPS for the example is shown in Figure 4.…”

“…Register files are increasingly being used as storage elements in modern VLSI systems [1,4,3,6]. The motivation for preferring register files to scratch registers 1 Research was conducted when the authors were at Indian Institute of Technology, Delhi, India.…”

“…This can lead to a significant saving in chip area. Several authors have considered the problem of optimal utilization of register files in data path synthesis [1,4,3,6]. This problem is usually solved in two steps.…”

“…The method of [3] is not practical for large examples since the number of variables involved in the integer linear program is extremely large. Chen [4] presented a backtracking algorithm for assignment of registers to register files, with the objective of minimizing the number of register files. The author does not perform grouping of registers, and the derivation of the datapath architecture is not automatic.…”