Using reconfigurability to achieve real-time profiling for hardware/software codesign

Abstract

Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces many problems, one being how to partition a single design for the two platforms to achieve the best performance with the least effort. Since the latest FPGA technology allows the integration of soft or hard CPU cores with dedicated logic on a single chip, this presents new opportunities for addressing hardware/software codesign issues in the FPGA design process by utilizing the reconfigurable environment.This paper introduces SnoopP, a non-intrusive, real time, profiling tool. The user is able to obtain a clock cycle accurate profile of the real time performance of a software program running on a soft-core processor instantiated on an FPGA. SnoopP is an essential tool for hardware/software codesign on a reconfigurable platform. It allows the user to quickly obtain accurate profiling information that may greatly influence the partitioning of the design.

Low-cost hardware profiling of run-time and energy in FPGA embedded processors

“…The question that naturally arises is how to determine the counter associated with a particular function. Prior hardware profilers, such as SnoopP [24], use a large number of comparators to associate PC address ranges with individual counters. A key innovation in LEAP is the use of perfect hashing in hardware to associate functions with counters, resulting in significantly less hardware overhead when compared to previously published work.…”

“…SnoopP [24] is an FPGA-based hardware profiler designed for use with the Xilinx MicroBlaze soft processor [30]. It allows arbitrary code regions to be profiled for cycle counts.…”

“…The use of hashing leads to considerably smaller overhead versus previously-published hardware profiler designs. Specifically, relative to SnoopP [24] (a hardware profiler for FPGA-based processors), our design requires up to 18× less area and 8.6× less energy. Moreover, our design is extensible in that it can be easily adapted to profile different run-time characteristics, including instruction and cycle counts, cache stalls, pipeline stalls, and energy consumption.…”

Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures

“…Shannon and Chow [31] have developed SnoopP, a non-intrusive snooping profiler. SnoopP supports the measurement of the number of clock cycles spent executing specified code regions.…”

“…Section 3 describes the reconfigurable platform that is the vehicle for the research and experiments reported in this paper. In Section 4, we illustrate our approach for collecting statistics by showing how to collect timing information using an FPGA-deployed circuit; here we extend recent work [31] on using reconfigurable architectures for profiling. Our approach does not instrument software at all, but relies instead on reconfigurable hardware and replicated logic to monitor the cycles spent in each code segment of interest.…”