Using simulation and satisfiability to compute flexibilities in Boolean networks

Abstract

Abstract-Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications.

ABC: An Academic Industrial-Strength Verification Tool

“…Aiming to find better ways to manipulate multi-valued relations, we experimented with new logic representations, such as AIGs, and found that, in addition to their use in formal verification, they can replace more-traditional representations in logic synthesis. As a result of our experiments with MVSIS, we developed a methodology for tackling problems, which are traditionally solved with SOPs [35] and BDDs [37], using a combination of random/guided simulation of AIGs and Boolean satisfiability (SAT) [25].…”

Automating Logic Transformations With Approximate SPFDs

“…Like all BDD-based techniques, computing BDDs of some types of circuits (e.g., multipliers) may not be memory efficient [16]. The SAT-based approach alleviates the memory issue with BDDs, but it can be computationally intensive to obtain all the minterm pairs that need to be distinguished [16].…”

“…In the past, Sets of Pairs of Functions to be Distinguished (SPFDs) have proved to provide additional degrees of flexibility during logic synthesis [14], [15]. However, computing SPFDs can be computationally expensive in terms of runtime and memory [16]. To address this problem, aSPFDs approximate the information contained in SPFDs using the results of test-vector simulation.…”

A Generalized and Unified SPFD-Based Rewiring Technique

“…Consider the graph in Figure 2, which represent local SP F D A at a node with 2 inputs. The bipartition in Figure 2a, representing OR, propagates only (00,01), (00,10), (00,11) but not (01,10), (10,11), (01,11). However, XOR, bipartition in Figure 2b, propagates (00,01), (00,10), (11,01), (11,10).…”