Using Sysml for Identification and Refinement of Machinery Safety Properties

Evrot, Dominique; Pétin, Jean-François; Morel, Gérard; Lamy, Pascal

doi:10.3182/20070613-3-fr-4909.00024

Cited by 4 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Kawahara et al 2009 proposed an extension of SysML, including continuoustime behavior based on co-simulation of SysML and MATLAB/Simulink. A method was proposed by Evrot et al 2007 andPetin et al 2010 identifying safety properties by formal verification for systems modeled by SYSML. Any type of model checkers, like B-language (Turner et al 2007), UPPAAL (Behrmann et al 2006) and other DES model checkers could be used to formally verify the safety properties of the system and also mapped information and combined SysML with general formal models for verification of safety requirements.…”

Section: Introductionmentioning

confidence: 99%

Interface between SysML and Sequence Planner Language for Formal Verification

Kanthabhabhajeya

Berglund

Falkman

et al. 2013

INCOSE International Symp

View full text Add to dashboard Cite

This paper presents a method and software for interfacing Systems Modeling Language (SysML) and Sequence Planner Language (SPL). Exchange of information between different software tools is of major interest for modern manufacturing industries from early design to final implementation. SysML, with its structure as a common platform, can then be interfaced with other domain-specific modeling tools to achieve information exchange. This paper presents a method to interface SysML with a recently introduced language for operation sequences called Sequence Planner Language (SPL). By this method, necessary information from behavioral constructs of SysML model are extracted and structured in SPL. This language, being a formal, graphical language,can be used to formally verify the system for any blocking states. An academic and an industrial model developed in SysML are tested using the interface implementation and the results show that information from SysML can be visualized in SPL and formally verified to have no blocking states.

show abstract

Section: Introductionmentioning

confidence: 99%

Interface between SysML and Sequence Planner Language for Formal Verification

Kanthabhabhajeya

Berglund

Falkman

et al. 2013

INCOSE International Symp

View full text Add to dashboard Cite

show abstract

Applying a Def-Use Approach on Signal Exchange to Implement SysML Model-Based Testing

Ambert

Bouquet

Lasalle

et al. 2013

Modelling Foundations and Applications

View full text Add to dashboard Cite

International audienceModel-Based Testing (MBT) uses a model of the System Under Test as reference to automatically derive test cases. Since it is often not reasonable to cover all the behaviours formalized in the model, coverage criteria are applied to select a relevant subset of model behaviours. In this paper, we propose a dedicated test coverage criterion, based on Def-Use criteria on signal exchange, to implement MBT approach from Systems Modeling Language (SysML) test models to validate mechatronic systems. This novel criterion is introduced and the relevance of the approach from SysML models is discussed regarding results obtained with a dedicated MBT toolchain implementing this criterion

show abstract