Using the same type of IP-cores in the Virtex-6 family FPGA-architecture for distributed image processing

Abstract

Distributed image processing in real time is a relevant task. An effective solution to this problem at the hardware level is possible on the basis of creating prototypes of devices on FPGA. In this regard, the paper solves the problem of distributed computation of two-dimensional fast Fourier transform (TDFFT) based on the same type of IP-cores implemented in the architecture of the Virtex-6 family_FPGA-architecture. The possibility of distributed implementation of each of the stages of the TDFFT, performed using four transformations of the “butterfly” type_(TrB) over four elements of the processed data array, is shown. When using a specialized CAD-system, estimates of the time and hardware complexity of the IP-core implementing TrB are_obtained. The estimated operating frequency of this_IP-core is approximately 108 MHz. Hardware complexity estimates by the number of configurable elements involved in the Virtex-6 family_FPGA-architecture are determined. TrB must be performed over an_array of N 2 elements a · N 2/4 once, where a = log2 N is the number of TDFFT stages, and N = 2 k . The ability to parallelize the specified operations at each of a stages by using_IP-cores that implement four TrB is shown. The results can be used to estimate hardware and time costs for distributed TDFFT execution over a square data array N × N - dimension.