Using Xilinx System Generator for Real Time Hardware Co-simulation of Video Processing System

Saidani, Taoufik; Atri, Mohamed; Dia, D.; Tourki, Rached

doi:10.1007/978-90-481-8776-8_20

Cited by 17 publications

(8 citation statements)

References 8 publications

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“…Unlike other designs where IPs are directly translated by cogeneration and co-simulation tools with system generator or dsp-builder [13]- [15], this design uses two parts combining hardware and software.…”

Section: Co-design Methodolgy Implementationmentioning

confidence: 99%

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

Fayçal

Ziet

Benoudjit

2021

IJEECS

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This paper presents an FPGA image segmentation-binarization system based on Iterative Self Organizing DATA (ISODATA) threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chip. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPC-builder or QSYS for the integration of NIOS-system, and NIOS-II-STB-ECLIPSE for the software program with eclipse c++ langage.

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Section: Co-design Methodolgy Implementationmentioning

confidence: 99%

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

Fayçal

Ziet

Benoudjit

2021

IJEECS

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“…where Ω , Ω , Φ, and Γ are chosen as positive constants [73], B is considered as the positive bound of the function , and Γ m and Γ M are considered as the bounds of the function at the second derivative of the sliding surface [74], witḧ Ω = ( , ) + ( , )̇ (49) To guarantee the convergence of the sliding surface to zero in the presence of disturbances and uncertainties, Table abc Induction Motor the functions ( , ) and ( , ) must verify the following conditions: Φ ≥ | | Γ ≥ ≥ Γ > 0. The reference of the torque generated by the sliding mode controller can be expressed as follows:…”

Section: Synthesis Of Super-twisting Rotor Speed Controllermentioning

confidence: 99%

“…Nevertheless, programming the VHDL or Verilog requires a lot of prototyping time which consequently increases the system cost. To overcome this problem, a Xilinx System Generator (XSG) toolbox is proposed in this work to automatically generate the VHDL code and the bitstream file [48,49]. The toolbox XSG is developed by Xilinx to be integrated into a Simulink environment and helps the designer rapidly implement control algorithms of the FPGA circuits [50].…”

Section: Introductionmentioning

confidence: 99%

Robust Direct Torque Control with Super‐Twisting Sliding Mode Control for an Induction Motor Drive

2019

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A field-programmable gate array- (FPGA-) based nonlinear Direct Torque Control (DTC) associated with Space Vector Modulation (SVM), Input-Output Feedback Linearization (IOFL), and second-order super-twisting speed controller is proposed to control an induction motor drive. First, the nonlinear IOFL is proposed to achieve a decoupled flux and torque control and the SVM technique is used to control the inverter switching frequency which reduces the torque ripples and noise. Next, to enhance the speed regulation, a super-twisting speed controller is added to an SVM-DTC-IOFL scheme. The nonlinear SVM-DTC-IOFL ensures a high dynamic response, good robustness under the external load disturbances. The Lyapunov theory is used to analyze the system stability. Then, this paper presents the interest of implementing the suggested SVM-DTC-IOFL using a Field-Programmable Gate Array (FPGA) circuit. The main interest of the FPGA-implementation is the reduction of the control loop delay, which is evaluated to a few microseconds, thanks to the parallel processing offered by the FPGA. The performances of the proposed control algorithm are investigated by digital simulation using the Xilinx system generator tool and an experimental implementation utilizing an FPGA-Virtex-5-ML507.

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“…It takes the abstraction level slightly higher. It uses the Mathworks Simulink with a list of specific Xilinx building blocks, which can be used to create designs optimized for Xilinx FPGA's [4]. The Matlab workspace can be used during simulation.…”

Section: Design Flowmentioning

confidence: 99%

“…The hardware implementation offers also parallelism and it reduces the processing time. Our algorithm is encoded using XSG, which has been the tool of many researchers in several areas [3,4]. It is a graphical interface added to Matlab Simulink.…”

Section: Introductionmentioning

confidence: 99%

Real Time Implementation of Detection of Bacteria in Microscopic Images Using System Generator

Ladgham¹

2012

J Biosens Bioelectron

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This paper outlines efficient hardware architecture of detection of bacteria and alga in microscopic images, using Xilinx System Generator (XSG). XSG is a high-level design tool based on blocks. It gives bit and cycle accurate simulation. The approach of detection used is the Hough transform. The latter is a very efficient approach of location of parametric curves in an image, especially lines. System was implemented on Virtex-V FPGA. To demonstrate the quality of the system, some experiments on microscopic images are given.

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Using Xilinx System Generator for Real Time Hardware Co-simulation of Video Processing System

Cited by 17 publications

References 8 publications

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

Robust Direct Torque Control with Super‐Twisting Sliding Mode Control for an Induction Motor Drive

Real Time Implementation of Detection of Bacteria in Microscopic Images Using System Generator

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