UTBB FDSOI scaling enablers for the 10nm node

Grenouillet, L.; Liu, Q.; Wacquez, R.; Morin, P.; Loubet, N.; Cooper, D.B.; Pofelski, Alexandre; Weng, Wen Jian; Bauman, Fred; Gribelyuk, M.; Wang, Y.; Salvo, B. De; Gimbert, J.; Cheng, K.; Tiec, Y. Le; Chanemougame, D.; Augendre, E.; Maitrejean, S.; Khakifirooz, A.; Kuss, J.; Schulz, R.; Janicki, C.; Lherron, B.; Guillaumet, S.; Rozeau, O.; Chafik, F.; Bataillon, J.-L.; Wu, Tian-Li; Kleemeier, W.; Celik, M.; Faynot, O.; Sampson, R.; Doris, B.; Vinet, M.

doi:10.1109/s3s.2013.6716546

Cited by 21 publications

(8 citation statements)

References 2 publications

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“…Because of the exponential increase in gate leakage current, the scaling of planar MOSFETs has encountered a fundamental limitation below the 65 nm technology node. To overcome this obstacle, the silicon-on-insulator (SOI), ultrathin body (UTB), and high-k dielectric have been introduced in 45-32 nm node production [2]. To bring 22-7 nm node devices into industrial production, the Si non-planar transistor structures were introduced as a possible replacement for the planar MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Comparative Characterization of NWFET and FinFET Transistor Structures Using TCAD Modeling

2022

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A complete comparison for 14 nm FinFET and NWFET with stacked nanowires was carried out. The electrical and thermal performances in two device structures were analyzed based on TCAD simulation results. The electro-thermal TCAD models were calibrated to data measured on 30–7 nm FinFETs and NWFETs. The full set of output electrical device parameters Ion, Ioff, SS, Vth, and maximal device temperature Tmax was discussed to achieve the optimum VLSI characteristics.

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Section: Introductionmentioning

confidence: 99%

Comparative Characterization of NWFET and FinFET Transistor Structures Using TCAD Modeling

2022

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“…With the scaling of the gate length, short-channel effects (SCEs), such as threshold voltage degradation and draininduced-barrier-lowering, increase the static power consumption of devices, leading to poor performance. Accordingly, UTBB-FDSOI technology has been proven to be a powerful solution to deal with SCEs, allowing the gate to lengthen to the 22 nm and even down to 10 nm nodes [11][12][13]. Moreover, it is suitable for low-power applications.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of 22 nm UTBB-FDSOI technology with an ultra-wide temperature range

Wang¹,

Bi²,

Bu³

et al. 2022

Semicond. Sci. Technol.

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The performance of the ultra-thin body and buried oxide (BOX) fully-depleted silicon-on-insulator (UTBB-FDSOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on a 22 nm technology node is investigated in this paper over an ultra-wide temperature range from 6 K to 550 K. The current-voltage (I-V) characteristics under wide temperature range conditions are shown, including the influence of the back-gate bias (Vbg). The important electrical parameters, such as threshold voltage (Vt), subthreshold swing (SS), ON-state current (Ion), and OFF-state current (Ioff), are extracted with temperature changes. From 550 K to 6 K, Vtincreased by 0.21 V, Ioff decreased nearly 6 orders of magnitude, and the gate-induced drain leakage (GIDL) current decreased by nearly 8 orders of magnitude. The main physical mechanisms for the changing electrical performance with temperature are the variation of carrier concentration, mobility, and energy band. By utilizing a technology computer-aided design (TCAD) simulation, the temperature dependence of the device performance is discussed and analyzed.

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“…The ultra-thin body ultra-thin box (UTBB) SOI MOSFET with the lightly-doped channel is demonstrating a high advantage for ultimate MOSFET scaling because of its dramatic suppression of short-channel effects (SCEs) (Young 1989;Grenouillet et al 2013), and its superiority of low-power high-speed application (Haond 2014;Stephane and Thomas 2016). The SCEs, which mainly includes the threshold voltage roll-off, the drain induced barrier lowering (DIBL), and the subthreshold swing degradation, is the major barrier for MOSFET downscaling.…”

Section: Introductionmentioning

confidence: 99%

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

et al. 2017

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An inspiring UTBB SOI MOSFET structure with enhanced immunity to the drain-induced barrier lowering (DIBL) is analyzed. The structure includes the dual-gates in the lateral direction. The voltage difference is applied between the dual-gates, through which the electrostatic potential and the energy band along the channel are modified and the electrical performance is boosted. The electrical characteristics are investigated by measuring the electron concentration, the conduction band energy level, and the potential at the front-surface. The impact of the negative voltage bias applied to the right gate on the performance of the new device is studied, and compared to that of the conventional ultra-thin body ultra-thin box silicon-on-insulator (UTBB SOI) devices. The results reveal that the undesirable DIBL values are lower in this innovative device than that in the conventional UTBB SOI MOSFET.

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UTBB FDSOI scaling enablers for the 10nm node

Abstract: UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.

Cited by 21 publications

References 2 publications

Comparative Characterization of NWFET and FinFET Transistor Structures Using TCAD Modeling

Comparative Characterization of NWFET and FinFET Transistor Structures Using TCAD Modeling

Characteristics of 22 nm UTBB-FDSOI technology with an ultra-wide temperature range

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

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