2020
DOI: 10.1109/tc.2019.2936477
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Utilization-Tensity Bound for Real-Time DAG Tasks under Global EDF Scheduling

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Cited by 21 publications
(5 citation statements)
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“…Previously, works on CIM architectures have only supported the inference of the DNN. Some of the works have been conducted for the in situ training process on-chip, based on the SRAM [68,69] and RRAM [70][71][72]. The energy-efficient feed forward propagation and backpropagation can be realized in these architectures.…”
Section: D Nand-based Fefet For Trainingmentioning
confidence: 99%
“…Previously, works on CIM architectures have only supported the inference of the DNN. Some of the works have been conducted for the in situ training process on-chip, based on the SRAM [68,69] and RRAM [70][71][72]. The energy-efficient feed forward propagation and backpropagation can be realized in these architectures.…”
Section: D Nand-based Fefet For Trainingmentioning
confidence: 99%
“…The drawback of capacity augmentation bound is that it gives the same threshold for both normalized utilization and tensity, i.e., a task set with small normalized utilization but maximum tensity slightly exceeding capacity augmentation bound cannot pass the schedulability test even it is easy to be scheduled. From this view, another metric named utilizationtensity bound which aims to have asymmetric thresholds for normalized utilization and tensity on unit-speed processors are derived in [12]. Instead of deriving schedulability conditions on speed-s processors and then transforming them to speed-1 processors, conditions to guarantee schedulability on unitspeed processors for G-EDF are directly derived by obtaining the "unit-speed version" of Lemma 3 and Lemma 4: Lemma 7 ( [12]).…”
Section: B Utilization-tensity Boundmentioning
confidence: 99%
“…From this view, another metric named utilizationtensity bound which aims to have asymmetric thresholds for normalized utilization and tensity on unit-speed processors are derived in [12]. Instead of deriving schedulability conditions on speed-s processors and then transforming them to speed-1 processors, conditions to guarantee schedulability on unitspeed processors for G-EDF are directly derived by obtaining the "unit-speed version" of Lemma 3 and Lemma 4: Lemma 7 ( [12]). For any task τ i and t > 0, it holds…”
Section: B Utilization-tensity Boundmentioning
confidence: 99%
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