2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
DOI: 10.1109/vlsit.2002.1015389
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UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect

Abstract: UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHF', HP, MP, Over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the requirement for various performance, multi-V, multi-thickness gate-oxide process, low-leakage gate &electric are incorporated in FEOL. To suppress RC increase compared to previous generation, low-k (KefF3.1) interlayer &electric and Cu interconnect dual damascene are incorp… Show more

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“…(1) (2) and are the power spectra for Gaussian and exponential autocorrelation functions, respectively. where is the discrete spacing used for the line and .…”
Section: Simulation Approachmentioning
confidence: 99%
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“…(1) (2) and are the power spectra for Gaussian and exponential autocorrelation functions, respectively. where is the discrete spacing used for the line and .…”
Section: Simulation Approachmentioning
confidence: 99%
“…N THE past couple of years, MOSFETs have reached deep decananometer (sub 50-nm) dimensions with 40-50-nm physical gate length devices developed now for the 90-nm technology node [1], [2], 35-nm transistors ready for mass production in 2-3 years time [3] and 10-nm MOSFETs with conventional architecture demonstrated in a research environment [4]. Intrinsic parameter fluctuations play an increasingly important role in such devices at a time when the fluctuation margins shrink due to reduction in supply voltage and increased transistors count per chip.…”
mentioning
confidence: 99%
“…N the past couple of years, MOSFETs have reached decananometer (between 10 and 100 nm) dimensions with 40-50 nm physical gate length devices that are available now in the 90-nm technology node [1], [2], 35-nm transistors ready for mass production in 2 to 3 years time [3] and 15 nm [4], and even 10 nm [5] MOSFETs with conventional architecture demonstrated in a research environment. The 2001 edition of the International Technology Roadmap for Semiconductors forecasts that the MOSFET will become a nanometer scale (i.e.…”
mentioning
confidence: 99%