V-band CMOS injection-locked frequency tripler using differential harmonic current injection technique

Abstract

This letter presents a V-band CMOS injection-locked frequency tripler (ILFT) fabricated in a standard 90-nm CMOS process. By employing a differential harmonic current injection technique, a frequency doubler (2f 0 ) realized in the connected source terminal of injection transistors is to mix with injection signals (f 0 ) through injection transistors, and output signals (3f 0 = 2f 0 ? f 0 ) are obtained from output buffers. The proposed ILFT improves the locking range and power dissipation by adopting two cross-coupled transistor pairs, and strengthens the rejection ability of second-order harmonic by using a resonator network. The proposed ILFT has the free-running frequency of 62.49 GHz and locking ranges of 61.2 to 64.2 GHz as input injection signals from 20.4 to 21.4 GHz at an input power level of 0 dBm. The proposed ILFT core consumes 7.48 mW from a supply voltage of 1.1 V.

Single-Stage Injection-Locked Frequency Sixtupler in CMOS Process

“…A frequency tripler (FT) can be constructed by an isolated frequency doubler followed by a mixer [16]. Here, L6, M3 and M4 construct a mixer-based frequency tripler [17], they act concurrently as a frequency doubler and a frequency tripler. A differential injection signal is applied to the gates of M3 and M4, even-order (2 nd & 4 th ) harmonics existing in the FET currents are added in phase at the common FET source and the odd-order harmonics are suppressed due to 180 o phase difference.…”