VACA: A high-performance variable-length adaptive CRC algorithm

Chi, Mucong; Li, Jun

doi:10.1109/pimrc.2017.8292219

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2019

2023

Publication Types

Select...

Article2

Other1

Relationship

Self Cite0

Independent3

Authors

Journals

Cited by 3 publications

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Parallel CRC optimisations on the x64 architecture: a per-partes method

Kašpar,

Šimeček

2023

International Journal of Parallel, Emergent and Distributed Sys

View full text Add to dashboard Cite

Parallel CRC optimisations on the x64 architecture: a per-partes method

Kašpar,

Šimeček

2023

International Journal of Parallel, Emergent and Distributed Sys

View full text Add to dashboard Cite

Exploring Various Levels of Parallelism in High-Performance CRC Algorithms

Chi

2019

IEEE Access

View full text Add to dashboard Cite

Modern processors have increased the capabilities of instruction-level parallelism (ILP) and thread-level parallelism (TLP). These resources, however, typically exhibit poor utilization on conventional cyclic redundancy check (CRC) algorithms. In this paper, various levels of parallelism in high-performance CRC algorithms are investigated. The main idea of the proposed algorithms is to make full utilization of modern processors, from the perspective of both instruction-level and thread-level parallelism. First, a finegrained algorithm executes the CRC computation in an interleaved manner, so that multiple independent data flows can be processed simultaneously. This algorithm allows instruction-level parallelism, which triples and doubles the performance of the existing slicing-by-4 and slicing-by-8 algorithms, respectively. Second, a coarse-grained algorithm can ideally deal with data in a parallel way by parallelizing a family of serial CRC generating algorithms. Therefore, this algorithm allows thread-level parallelism, which can make full use of multi-core computing capability. As a result, it achieves a speedup that is almost equal to the number of threads used. In addition, both fine-grained and coarse-grained algorithms can be applied together to achieve high throughput further. (This is an extended version of a paper that appeared at the 28th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC) in Montreal, QC, Canada, in 2017.) INDEX TERMS Cyclic redundancy check (CRC), fault detection, parallel algorithms.

show abstract

A Method of High-speed Parallel CRC Computation

Zhou,

Wang

2023

2023 5th International Conference on Electronic Engineering and Informatics (EEI)

View full text Add to dashboard Cite

VACA: A high-performance variable-length adaptive CRC algorithm

Cited by 3 publications

References 20 publications

Parallel CRC optimisations on the x64 architecture: a per-partes method

Parallel CRC optimisations on the x64 architecture: a per-partes method

Exploring Various Levels of Parallelism in High-Performance CRC Algorithms

A Method of High-speed Parallel CRC Computation

Contact Info

Product

Resources

About