VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits

Zervakis, Georgios; Koliogeorgi, Konstantina; Anagnostos, Dimitrios; Zompakis, Nikolaos; Siozios, Kostas

doi:10.1109/tvlsi.2019.2900160

Cited by 23 publications

(7 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, given (1) and (2), the power consumption highly depends on the circuit's area, voltage value, and switching activity. Hardware approximation techniques produce, mainly, simpler circuits (e.g., logic simplification [5]) to reduce the circuit's area and/or decrease the operating voltage value below its nominal value (e.g., Voltage Overscaling [23]). Simplifying the circuit can also result to lower delay, whereas reducing V decreases only the power consumption.…”

Section: Approximate Circuits With Reconfigurable Accuracymentioning

confidence: 99%

“…The authors in [22] propose a circuit partition algorithm to quantify the output significance of every gate and use this algorithm to guide and accelerate the application of [21]. Multi-level approximation is applied in [23] where a voltage-driven gate-level pruning is used to maximize the application of voltage over-scaling. However, during the pruning procedure, [21]- [23] consider only the error value and do not examine the impact of pruning a wire on the circuit's power.…”

Section: Related Workmentioning

confidence: 99%

“…Multi-level approximation is applied in [23] where a voltage-driven gate-level pruning is used to maximize the application of voltage over-scaling. However, during the pruning procedure, [21]- [23] consider only the error value and do not examine the impact of pruning a wire on the circuit's power. Therefore, the power efficiency of the generated designs remains unclear.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

2020

Self Cite

View full text Add to dashboard Cite

Leveraging the inherent error tolerance of a vast number of application domains that are rapidly growing, approximate computing arises as a design alternative to improve the efficiency of our computing systems by trading accuracy for energy savings. However, the requirement for computational accuracy is not fixed. Controlling the applied level of approximation dynamically at runtime is a key to effectively optimize energy, while still containing and bounding the induced errors at runtime. In this paper, we propose and implement an automatic and circuit independent design framework that generates approximate circuits with dynamically reconfigurable accuracy at runtime. The generated circuits feature varying accuracy levels, supporting also accurate execution. Extensive experimental evaluation, using industry strength flow and circuits, demonstrates that our generated approximate circuits improve the energy by up to 41% for 2% error bound and by 17.5% on average under a pessimistic scenario that assumes full accuracy requirement in the 33% of the runtime. To demonstrate further the efficiency of our framework, we considered two state-of-the-art technology libraries which are a 7nm conventional FinFET and an emerging technology that boosts performance at a high cost of increased dynamic power. INDEX TERMS Approximate computing, approximate design automation, dynamically reconfigurable accuracy, low power.

show abstract

Section: Approximate Circuits With Reconfigurable Accuracymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

2020

Self Cite

View full text Add to dashboard Cite

show abstract

“…A comparison among different multibit adders in terms of performance under VOS has been reported in [30]; it shows that 76% of the energy for an 8-bit ripple carry adder (RCA) is reduced when subject to only half of the supply voltage. Zervakis et al [31] introduce a voltage-driven functional approximation technique to reduce errors generated by VOS. A netlist pruning technique is proposed for designing cross-layer approximate arithmetic circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Zervakis et al . [31] introduce a voltage‐driven functional approximation technique to reduce errors generated by VOS. A netlist pruning technique is proposed for designing cross‐layer approximate arithmetic circuits.…”

Section: Introductionmentioning

confidence: 99%

Approximate computing using frequency upscaling

Huang¹,

Kumar²,

Abbas³

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This study presents frequency upscaling as a technique for developing error resilient arithmetic designs in approximate computing whereby the input signal frequency of the circuit is upscaled beyond its largest operating value in generating errors in the arithmetic operation while speeding up the computational throughput. This study initially presents the mathematical modelling of frequency upscaling for both exact and inexact full adders. An exhaustive simulation and evaluation of 4 and 8 bits subtraction followed by addition of two images and approximate discrete cosine transform (DCT) is pursued using exact and inexact circuits when subjected to the proposed technique. The results estimated using the proposed model show good agreement with the simulation results. The normalised mean error distance of subtraction using an inexact circuit is close to the exact value for different technology nodes. The peak signal-to-noise ratio (PSNR) results for the addition of two images show that the inexact full adder achieves a higher output image quality than the exact circuit when the frequency is scaled up. Also, in an approximate DCT, the input frequency of an inexact full adder can be scaled up significantly higher than an exact full adder without a significant decrease in PSNR value.

show abstract