Validation in a component-based design flow for multicore SoCs

Abstract

Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable this integration, we use a design approach called component based-design approach. In this approach, the validation of system integration takes most of design efforts. This paper presents an automatic method of SoCs design validation. Based on a generic simulation wrapper architecture, the presented method provides automatic generation of executable models throughout different stages of SoC design flow. A case study of validating a VDSL application shows the effectiveness of the method.

MP SoCs including optical interconnect: technological progresses and challenges for CAD tools design

“…The interconnections have to be simple, predictable and scaleable [2]. Future designs will contain an increasing number of application specific programmable units combined with complex memory infrastructures [15].…”

“…The researchers from Tima Laboratory define a new model for global representation of heterogeneous systems specification by automatic generation of cosimulation instances [15]. Here the heterogeneity is given by the co-existence of different modules described at different abstraction levels, using different specification languages.…”