Validation of selecting SP-values for fault models under proposed RASP-FIT tool

Khatri, Abdul Rafay; Hayek, Ali; Börcsök, Josef

doi:10.1109/intellect.2017.8277633

Cited by 3 publications

(3 citation statements)

References 37 publications

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“…1) Gate-level Designs: At gate abstraction level, the basic cell of the design is a logic gate. A logic circuit which contains a few hundreds of logic gates are typically designed at this level [4]. xor, bufif0, etc.…”

Section: A Code Parsing Technique In Rasp-fitmentioning

confidence: 99%

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RASP-FIT: A Fast and Automatic Fault Injection Tool for Code-Modification of FPGA Designs

Khatri¹,

Hayek²,

Börcsök³

2018

ijacsa

Self Cite

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Fault Injection (FI) is the most popular technique used in the evaluation of fault effects and the dependability of a design. Fault Simulation/Emulation (S/E) is involved in several applications such as test data generation, test set evaluation, circuit testability, fault detection & diagnosis, and many others. These applications require a faulty module of the original design for fault injection testing. Currently, Hardware Description Languages (HDL) are involved in improving methodologies related to the digital system testing for Field Programmable Gate Array (FPGA). Designers can perform advanced testing and fault S/E methods directly on HDL. To modify the HDL design, it is very cumbersome and time-consuming task. Therefore, a fault injection tool (RASP-FIT) is developed and presented, which consists of code-modifier, fault injection control unit and result analyser. However, in this paper, code modification techniques of RASP-FIT are explained for the Verilog code at different abstraction levels. By code-modification, it means that a faulty module of the original design is generated which includes different permanent and transient faults at every possible location. The RASP-FIT tool is an automatic and fast tool which does not require much user intervention. To validate these claims, various faulty modules for different benchmark designs are generated and presented.

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Section: A Code Parsing Technique In Rasp-fitmentioning

confidence: 99%

“…synthesis, translate, place & route, and then a bit-stream generation. Various fault injection tools have been devised in the past several years for FPGA-based designs, which work on different stages of the development flow [3], [4] as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

RASP-FIT: A Fast and Automatic Fault Injection Tool for Code-Modification of FPGA Designs

Khatri¹,

Hayek²,

Börcsök³

2018

ijacsa

Self Cite

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“…We selected a set-point value for each design and each fault model. The experimental way to obtain the sp-value is described in [21]. The procedure for / / O r i g i n a l d e s i g n module c17 ( N1 , N2 , N3 , N6 , N7 , N22 , N23 ) ; i n p u t N1 , N2 , N3 , N6 , N7 ; o u t p u t N22 , N23 ; w i r e N10 , N11 , N16 , N19 ;…”

Section: B Hardness Analysis: Identification Of Sensitive Nodesmentioning

confidence: 99%

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

Khatri¹,

Hayek²,

̈ok³

2018

ijacsa

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Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system's complexity makes the reliability evaluation extremely difficult and costly. Redundancy techniques are widely used to increase the reliability of such systems. These techniques provide a large area & time overheads which cause more power consumption and delay, respectively. An experimental evaluation method is proposed to find critical nodes of the FPGA-based designs, named "hardness analysis technique" under the proposed RASP-FIT tool. After finding the critical nodes, the proposed redundant model is applied to those locations of the design and the code is modified. The modified code is functionally equivalent and is more hardened to the soft-errors. An experimental setup is developed to verify and validate the criticality of these locations found by using hardness analysis. After applying redundancy to those locations, the reliability is evaluated concerning failure rate reduction. Experimental results on ISCAS'85 combinational benchmarks show that a min-max range of failure reduction (14%-85%) is achieved compared to the circuit without redundancy under the same faulty conditions, which improves reliability.

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Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool

Khatri

Hayek

Borscok³

2018

2018 IEEE 16th Intl Conf on Dependable, Autonomic and Secure Computing, 16th Intl Conf on Pervasive Intelligence and Computing,

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Validation of selecting SP-values for fault models under proposed RASP-FIT tool

Cited by 3 publications

References 37 publications

RASP-FIT: A Fast and Automatic Fault Injection Tool for Code-Modification of FPGA Designs

RASP-FIT: A Fast and Automatic Fault Injection Tool for Code-Modification of FPGA Designs

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool

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