Validation of Task Scheduling Techniques in Multithread Time Predictable Systems

Antolak, Ernest; Pułka, Andrzej

doi:10.1109/access.2023.3275437

Cited by 2 publications

(13 citation statements)

References 45 publications

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“…In recent years, the authors have been developing their original real-time system architecture [1,6,9,28,29]. The microarchitecture of the cores constituting the presented system is based on the instruction set architecture (ISA) of ARM family processors.…”

Section: Real-time System Architecturementioning

confidence: 99%

“…The microarchitecture of the cores constituting the presented system is based on the instruction set architecture (ISA) of ARM family processors. However, a special extension has been introduced to handle data exchange and execution time control [1], including the addition of such instructions as:…”

Section: Real-time System Architecturementioning

confidence: 99%

“…For tasks that do not communicate with other tasks, the valu zero. The other parameters (Mdur and Minindistance) are determined figuration of the system architecture [1] and are fixed for this con the number of clock cycles needed to perform a memory opera dependent tasks, i.e., those threads that exchange data with one Minindistance determines the minimal interval between two consec same thread in a pipeline processing cycle (measured using the n es), which allows for avoiding data and control hazards [3].…”

Section: Real-time System Architecturementioning

confidence: 99%

“…The authors of the paper also proposed their own original architecture for a timepredictable system, the latest version of which was presented in [1]. This solution is based on a multi-core regular structure and pipelined processing.…”

Section: Introductionmentioning

confidence: 99%

“…Different task scheduling options were also analyzed depending on additional externally imposed requirements and design constraints related to, among other things, power consumed, processing efficiency, or required resources. In their previous work [1], the authors presented an original environment for accurately measuring task execution time, which is a key parameter for time-predictable systems. They introduced the original Worst Case Timing Analyzer (WCTA), which allowed precise control of the timing of the designed system.…”

Section: Introductionmentioning

confidence: 99%

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Power Consumption Prediction in Real-Time Multitasking Systems

Antolak,

Pułka

2024

Electronics

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The paper presents a practical methodology for the prediction of power consumption of a multitask real-time system. The authors briefly recall the structure of the original multitasking time-predictable system. The system has a regular and scalable architecture. It consists of many cores based on pipeline processing with threads’ interleaving mechanism. In previous works, the authors have presented a number of issues related to the methodology of designing a time-predictable system and the scheduling of hardware threads with different design goals and constraints. The current article presents an accurate method for measuring the dynamic power dissipated in a system for various scenarios and the system configuration. The proposed approach is based on continuous monitoring of the power consumed by the FPGA, transmitting the measurements to the computer from the measuring device, and online analysis of the obtained results. The authors based their power estimation method on the original task frequency factor (TF). A theoretical analysis was made, and a series of practical experiments were carried out. The results obtained enable accurate estimation of the power requirements for the tasks performed in the real-time system. The presented technique can be useful during the design stage of multitasking real-time systems.

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Section: Real-time System Architecturementioning

confidence: 99%

Section: Real-time System Architecturementioning

confidence: 99%

Section: Real-time System Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Power Consumption Prediction in Real-Time Multitasking Systems

Antolak,

Pułka

2024

Electronics

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Fault-Tolerant Multitasking System Based on Interleaving of Threads

Antolak,

Pułka

2024

Electronics

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This paper presents an original approach to error correction in real-time systems. The proposed solution is based on the original multitasking system architecture, which was recently analyzed for energy. The authors have added a structure to correct random errors and distortions at the signal level, increasing reliability. The authors overview their original multitasking, time-predictable, multi-core system. The system has a regular structure with pipelined processing. The threads in each core are interleaved, eliminating the need for complex hazard control mechanisms. Previous works presented issues related to designing a predictable system and scheduling hardware threads with different design goals. The proposed fault detection method is based on scalable redundancy. Replicated processing units correct erroneous register file contents. The replication level can be adapted to current requirements. A mechanism for checking unused registers with “cycle stealing” is proposed with minimal impact on processing continuity. This paper presents the proposed hardware solution implemented in an FPGA device. Experiments using randomly generated errors showed that an additional structure can correct hardware errors. Furthermore, it was shown that the applied solution has a minimal impact on the system performance due to the use of thread interleaving and an error-checking and correction mechanism.

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Validation of Task Scheduling Techniques in Multithread Time Predictable Systems

Cited by 2 publications

References 45 publications

Power Consumption Prediction in Real-Time Multitasking Systems

Power Consumption Prediction in Real-Time Multitasking Systems

Fault-Tolerant Multitasking System Based on Interleaving of Threads

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