Valley-Coupled-Spintronic Non-Volatile Memories With Compute-In-Memory Support

Thirumala, Sandeep Krishna; Hung, Yi-Tse; Jain, Shubham; Raha, Arnab; Thakuria, Niharika; Raghunathan, Vijay; Raghunathan, Anand; Chen, Zhihong; Gupta, Sumeet Kumar

doi:10.1109/tnano.2020.3012550

Cited by 11 publications

(30 citation statements)

References 44 publications

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“…3. Addition schemes in STT-CiM series [26], [27], [28], ParaPIM series [29], [30], GraphS series [31], [32], [33] IMC designs and our proposed FAT.…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

“…Also, addition operations have replaced the multiplications for higher performance in TWNs, but the addition operations in existing IMC devices are not efficient. The mainstream STT-CiM series [26], [27], [28], ParaPIM series [29], [30], and GraphS series [31], [32], [33] designs are excellent traditional IMC architectures or application-specific accelerators, but their addition schemes are not efficient. They either need to wait for the carry propagating to the last bit or write back the carry to the memory cells and read out the carry back and forth.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Zhu

Duong

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Convolutional Neural Networks (CNNs) demonstrate excellent performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity than BWNs, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient.In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of activations and weights and increase the parallelism across memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00× speedup, 1.22× power efficiency and 1.22× area efficiency compared with a State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02× speedup and 12.19× energy efficiency compared with ParaPIM on networks with 80% average sparsity.

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“…3. Addition schemes in STT-CiM series [26], [27], [28], ParaPIM series [29], [30], GraphS series [31], [32], [33] IMC designs and our proposed FAT.…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Zhu

Duong

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…3. Addition schemes in STT-CiM series [29], [30], [31], ParaPIM series [32], [33], GraphS series [34], [35], [36] IMC devices and our proposed FAT.…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

“…Also, addition operations have replaced the multiplications for higher performance in TWNs, but the addition operations in existing IMC devices are not efficient. The mainstream STT-CiM series [29], [30], [31], ParaPIM series [32], [33] and GraphS series [34], [35], [36] devices are excellent IMC designs in general-purpose and application-specific domains, but their addition schemes are not efficient. They either need to wait for the carry propagating to the last bit or write back the carry to the memory cells and read out the carry back and forth.…”

Section: Introductionmentioning

confidence: 99%

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Zhu,

Duong,

Chen

et al. 2022

Preprint

View full text Add to dashboard Cite

Convolutional Neural Networks (CNNs) demonstrate great performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient.In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to the memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of both activations and weights and increase the parallelism of memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00× speedup, 1.22× power efficiency and 1.22× area efficiency compared with State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02× speedup and 12.19× energy efficiency compared with ParaPIM on networks with 80% sparsity.

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“…However, when entering into the deca-nanometer regime CMOS downscaling becomes more difficult due to: (i) leakage wall 4,5 , (ii) reliability wall 6 , and (iii) cost wall 4,6 , which suggests the near end of Moore's law. As a result, different technologies, e.g., graphene [7][8][9][10][11] , memristor [12][13][14][15][16] , spintronics [17][18][19][20][21] have been explored in an attempt to meet the exponentially increasing computing market demands 22 .…”

Section: Introductionmentioning

confidence: 99%

Multifrequency Data Parallel Spin Wave Logic Gates

et al. 2021

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By their very nature, Spin Waves (SWs) with different frequencies can propagate through the same waveguide, while mostly interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road towards hardware replication free parallel data processing.In this paper, we take advantage of these features and propose a novel data parallel spin wave based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input Majority gates are implemented and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and Majority implementations, respectively. To get inside on the practical implications of our proposal we compare the byte-wide gates with conventional functionally equivalent scalar SW gate based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input Majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold based detection based gates.

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Valley-Coupled-Spintronic Non-Volatile Memories With Compute-In-Memory Support

Cited by 11 publications

References 44 publications

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Multifrequency Data Parallel Spin Wave Logic Gates

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