VaMV: Variability-aware Memory Virtualization

Abstract

Power consumption variability of both on-chip SRAMs and off-chip DRAMs is expected to continue to increase over the next decades. We opportunistically exploit this variability through a novel Variabilityaware Memory Virtualization (VaMV) layer that allows programmers to partition their application's address space (through annotations) into virtual address regions and create mapping policies for each region. Each policy has different requirements (e.g., power, fault-tolerance) and is exploited by our dynamic memory management module (VaMVisor), which adapts to the underlying hardware, prioritizes the memory resources according to their characteristics (e.g., power consumption), and selectively maps data to the best-fitting memory resource (e.g., high-utilization data to low-power memory space). Our experimental results on embedded benchmarks show that VaMV is capable of reducing dynamic power consumption by 63% on average while reducing total execution time by an average of 34% by exploiting: 1) SRAM voltage scaling, 2) DRAM power variability, and 3) Efficient dynamic policydriven variability-aware memory allocation.

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

“…Bathen et al [24] recently proposed the introduction of a hardware engine to virtualize on-chip and off-chip memory space to exploit the variation in the memory subsystem. These designs require changes to existing memory hardware, incurring additional design cost.…”

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

“…Variation in memory power consumption, error, and latency characteristics can be handled by allowing the run time system to select different application memory layout, initialization, and allocation strategies for different application requirements. An architecture for hardware-assisted variability-aware memory virtualization (VaMV) that allows programmers to exploit application-level semantic information [56] by annotating data structures and partitioning their address space into regions with different power, performance, and fault-tolerance guarantees (e.g., map look-up tables into low-power fault-tolerant space or pixel data in low-power nonfault-tolerant space) was explored in [57]. The VaMV memory supervisor allocates memory based on priority, application annotations, device signatures based on the memory subsystem characteristics (e.g., power consumption), and current memory usage.…”

Variability-aware memory management for nanoscale computing

“…To address and exploit these variations, [5] proposed the concept of VaMV: a power variation-aware memory virtualization layer for scratchpad memory-based chip-multiprocessors. The goal of the VaMV layer is to allow programmers to opportunistically exploit variability across various levels of the memory hierarchy through annotations in order to reduce power consumption.…”