Van der Waals Epitaxy of Horizontally Orientated Bismuth Iodide/Silicon Heterostructure for Nonvolatile Resistive‐Switching Memory with Multistate Data Storage

Abstract

The film quality of insulators significantly affects performance of resistive random‐access memories (RRAMs), particularly in current leakage and degradation. In this study, a facile and practical method is employed to achieve the van der Waals epitaxy of bismuth iodide (BiI3) on silicon by using a self‐assembled monolayer of octadecyltrichlorosilane (OTS) as a buffer layer. The BiI3 layer is compact and has high crystallinity, a pinhole‐free, and compact surface; every BiI3 crystal is horizontally aligned with OTS–Si substrate. The RRAMs with the Si++/OTS/BiI3/Au structure exhibit excellent resistive switching properties with a very high on/off ratio of 109, long‐term stability for data retention, high endurance in write–erase cycles, and multistate information storage capacity. The crystal orientation, anisotropic carrier transport, morphology, deposition rate, and roughness considerably influence the resistive switching results. These are thoroughly investigated by analyzing the current–voltage characteristics at various temperatures, scanning electron microscope, atomic force microscope, X‐ray photoemission spectroscopy, and X‐ray diffraction patterns. It is proposed that the resistive switching mechanisms is caused by the iodine ion migration, which changes the valence charge of bismuth. This leaves a partially formed conductive metallic bismuth filament in the BiI3 layer under the electrical field that enables multistate data storage.

Reliable BiI3-Based Resistive Random-Access Memory Devices with a High On/Off Ratio

“…When the voltage exceeds 0.1 V, the slope of the log–log scale I – V curves is 2.11, where space charge limited conduction dominates. These results are consistent with the previous reports …”

“…The RRAM device was vertically stacked with the structure of the bottom electrode (Ag), BiI 3 (150 nm), and top electrode (Au), as shown in Figure b. Since the surface roughness of BiI 3 is a factor that might cause a large first reset voltage, the morphology of the BiI 3 film needs to be studied first . The BiI 3 film deposited on the Ag substrate without the annealing process presents a porous and uneven morphology with a root-mean-square roughness of 14.72 nm, and there are lots pin holes in the surface of BiI 3 thin films, as shown in Figure S1.…”

“…Since the surface roughness of BiI 3 is a factor that might cause a large first reset voltage, the morphology of the BiI 3 film needs to be studied first. 50 The BiI 3 film deposited on the Ag substrate without the annealing process presents a porous and uneven morphology with a root- mean-square roughness of 14.72 nm, and there are lots pin holes in the surface of BiI 3 thin films, as shown in Figure S1. The pin holes inside the device will generate defect area and result in the leakage current while the device is applied bias.…”

Room-Temperature Fabricated Multilevel Nonvolatile Lead-Free Cesium Halide Memristors for Reconfigurable In-Memory Computing

“…In recent studies, halide-based memristors, including various halide perovskites and metal halides as resistive switching materials, have emerged as prominent candidates, providing low set/reset voltages of hundreds of millivolts and high on/off ratios; nevertheless, they have usually suffered from several issues, such as a lack of nonvolatile multilevel states, high variation of switching voltages, and poor endurance (see Table ). − In addition, to yield appropriate halide perovskite structures a thermal-induced phase transformation is essential, rendering them incompatible with the modern back-end-of-line processes used in IC integration and hindering three-dimensional (3D) networking. , Combined with their eco-unfriendly lead component and toxic solvent-based fabrication, several critical challenges remain as obstacles against their application. Therefore, the quest remains for an all-around halide material that can fulfill all of the key merits.…”

“…Although it is possible to exploit the entropy of CBMs in encryption applications, , giving another perspective to their developments, such randomness remains undesirable for their applications as storage units. In attempt to regulate the dynamics of CFs, recent studies have focused mainly on strategies involving doping, defect engineering, nanostructure engineering, and heterostructure design. ,− In contrast to those previous approaches, in this present study we developed a solution by introducing a buffer layer MoO X to effectively modulate the rupture of the CFs and create more conductive paths in the active layer, thereby improving the reliability of memristors with forming-free, ultralow operating voltages.…”