Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations

We fabricated JunctionLess (JL) and Inversion-Mode (IM) monocrystalline nanowire NMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junctionless transistors for analog applications: A VT =1.4mV.µm matching, Av0=62dB gain (L=200nm), f T =126GHz cutoff frequency and f MAX =182GHz maximum operating frequency. Junctionless transistor performances even exceed those of IM-FETs in terms of back-bias capability, low-frequency noise, hot-carrier degradation and f MAX. This is explained by JL physics combining characterization and TCAD simulations: channel length modulation, bulk conduction and high channel depth sensitivity to back bias.

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Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations

Cited by 3 publications

References 23 publications

A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

Investigation of Two Bits With Multistate Antifuse on nMOS Poly-Silicon Junctionless GAA OTP

Comparative experimental study of junctionless and inversion-mode nanowire transistors for analog applications

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