Variable Precision Multiplier for CNN Accelerators Based on Booth Algorithm

Abstract

As the utilization of CNN increases, many studies on lightweight, such as pruning, quantization, and compression, have been conducted to use CNN models in servers and edge devices. Studies have revealed that quantization greatly reduces the complexity of CNN models while lowering accuracy to a negligible level. CNN models with bit precision lowered from the existing 64/32 floating point to 16, 8, and 4 fixed points are being announced. Therefore, this paper proposes a variable precision multiplier that can select between 16 bits and 8 bits of precision. It consists of four 8-bit booth multipliers. When 16-bit multiplication is selected, the final product is calculated from four partial products, and when 8-bit multiplication is selected, four multiplications are possible simultaneously. The proposed multiplier was designed with Verilog HDL, and its function was verified in ModelSim. And it was synthesized for Altera Cyclone III EP3C16F484C6 using Quartus II 13.1.0 Web Edition. The proposed variable multiplier has increased combinational logic compared to general 8-bit/16-bit booth multipliers, and the clock speed is reduced by 65% and 82%, respectively. However, it can process four 8-bit multiplications within 1.68 times of normal 8-bit multiplication processing time and can process 16-bit multiplication within 75% of the normal 16-bit multiplication processing time. Therefore, the proposed multiplier is expected to increase speed and energy efficiency by selecting bit precision according to the layer in the CNN model.