Variation Aware Design of Post-Silicon Tunable Clock Buffer

Abstract

Process variation is a major limiting factor in designing high performance circuits in advanced CMOS technologies. Over optimizing data paths to provide adequate design margin is leading to increased area and power overhead. In this work, we present a variation aware design of Post-Silicon Tunable (PST) clock buffers to redistribute clock skew and mitigate impact of process variation on chip performance. Conventional PST buffers are designed for linear delay values. We estimate a set of non-linear delay intervals of PST buffer based on slack variation in each critical path. The configuration device sizes are mapped to the non-linear delay intervals using a set of equality conditions and solved using Linear Programming (LP). The variation aware device sizing provides many small delay intervals within one standard deviation of slack distribution and fewer large delay intervals to compensate for larger slack variations. This helps in optimal tuning of PST buffers to fix hold time, as well as better skew distribution to achieve maximum possible performance in a chip. The proposed PST buffer design technique was implemented for ISCAS'89 benchmark circuits. Non-linear delay PST buffers improve performance binning yield by more than 4%. They also provide optimum buffer circuits with an area reduction of 30% and leakage power reduction of 20%. The proposed technique can be implemented by designing dedicated buffers for each critical path or using a smaller set of pre-designed buffers with non-linear delay values.