Variation-aware task scheduling and power mode selection for MPSoC power optimization

Abstract

Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by simulating the algorithm with two different statistical analysis methods called Monte Carlo and Event-Reference-Table-based method. We have shown that by considering both leakage and frequency variation during the simultaneous selection of task scheduling and power mode switching policies, our algorithm achieves significant improvement over conventional methods.