Variation-aware voltage island formation for power efficient near-threshold manycore architectures

Stamelakos, Ioannis; Xydis, Sotirios; Palermo, Gianluca; Silvano, Cristina

doi:10.1109/aspdac.2014.6742907

Cited by 12 publications

(11 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The effect of the proposed technique can be decomposed into two factors: one is from MVMF, and the other is from CPM-based V/F tuning in the post-silicon stage. Therefore, we perform simulations for single-voltage single-frequency (SVSF), single-voltage multiplefrequency (SVMF) [6], multiple-voltage singlefrequency (MVSF) [7], and our multiple-voltage multiple-frequency (MVMF) with the pre-decision method or the tuning method. Fig.…”

Section: Resultsmentioning

confidence: 99%

“…1 shows an example of the VFI-based NTC manycore architecture with 64 cores, 16 VFIs, and two-level caches. For simplicity, the number of cores in every island is assumed to be equal, as in [6,7]. Each core in an island has a private level-1 instruction and data cache, and shares the last-level cache to construct intra-island architecture.…”

Section: Tunable Ntc Architecturementioning

confidence: 99%

“…We achieve this purpose by adapting the voltage and frequency of each VFI to the given inputs, namely, critical-path delay information from CPM, STC frequencies, and the number of VFIs. In the following derivation, we follow the equations and notation used in [6]. To maintain the STC performance in the NTC regime, highly parallelizable workloads should be adopted considering the trade-offs between the reduced clock frequency and the increased number of cores in the NTC.…”

Section: Descriptionmentioning

confidence: 99%

“…The authors in [6,7] present voltage island management methods to accommodate process variation in the architectural model during design; thereby, they exploit the potential energy efficiency gain. However, using a model-based pre-decision is not sufficient, because actual process variation occurs (systematically or randomly) during the chip manufacturing process.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li¹,

Kim²,

Heo³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage-and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiplevoltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Tunable Ntc Architecturementioning

confidence: 99%

Section: Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li¹,

Kim²,

Heo³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…The increase in execution time depends on the accuracy of processor idle time prediction. References [25,26] used Near Threshold Computing (NTC) to save processor energy consumption. Except for saving processor energy consumption, Refs.…”

Section: Related Workmentioning

confidence: 99%

More bang for your buck: Boosting performance with capped power consumption

Chen

et al. 2021

Tinshhua Sci. Technol.

View full text Add to dashboard Cite

Achieving faster performance without increasing power and energy consumption for computing systems is an outstanding challenge. This paper develops a novel resource allocation scheme for memory-bound applications running on High-Performance Computing (HPC) clusters, aiming to improve application performance without breaching peak power constraints and total energy consumption. Our scheme estimates how the number of processor cores and CPU frequency setting affects the application performance. It then uses the estimate to provide additional compute nodes to memory-bound applications if it is profitable to do so. We implement and apply our algorithm to 12 representative benchmarks from the NAS parallel benchmark and HPC Challenge (HPCC) benchmark suites and evaluate it on a representative HPC cluster. Experimental results show that our approach can effectively mitigate memory contention to improve application performance, and it achieves this without significantly increasing the peak power and overall energy consumption. Our approach obtains on average 12.69% performance improvement over the default resource allocation strategy, but uses 7.06% less total power, which translates into 17.77% energy savings.

show abstract

Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees

Stamelakos

Xydis²,

Palermo

et al. 2016

Near Threshold Computing

View full text Add to dashboard Cite

The power-wall problem driven by the stagnation of supply voltages in deep-submicron technology nodes, is now the major scaling barrier for moving towards the manycore era. Although the technology scaling enables extreme volumes of computational power, power budget violations will permit only a limited portion to be actually exploited, leading to the so called dark silicon. Near-Threshold voltage Computing (NTC) has emerged as a promising approach to overcome the manycore power-wall, at the expenses of reduced performance values and higher sensitivity to process variations. Given that several application domains operate over specific performance constraints, the performance sustainability is considered a major issue for the wide adoption of NTC. Thus, in this chapter, we investigate how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes. We propose three aggressive NTC voltage tuning and allocation strategies, showing that performance can be efficiently sustained or even optimized at the NTC regime. Finally, we show that NTC highly depends on the underlying workload characteristics, delivering average power gains of 65 % for thread-parallel workloads and up to 90 % for process-parallel workloads, while offering an extensive analysis on the effects of different voltage tuning/allocation strategies and voltage regulator configurations

show abstract

Variation-aware voltage island formation for power efficient near-threshold manycore architectures

Cited by 12 publications

References 28 publications

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

More bang for your buck: Boosting performance with capped power consumption

Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees

Contact Info

Product

Resources

About