Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits

Kwong, Joyce; Chandrakasan, Anantha P.

doi:10.1109/lpe.2006.4271799

Cited by 80 publications

(46 citation statements)

References 11 publications

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“…Due to the higher switching of the gates the optimal voltage occurs at a much low voltage for the CS adder because the leakage energy is reduced and an improvement in overall energy is achieved. It should be noted that in designing the adders only two input gates with fan-out limited to three and minimum sized transistors were employed in order to reduce leakage energy and to avoid circuit failure [9]. …”

Section: Minimum Energy Point Analysis Of Addersmentioning

confidence: 99%

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

Lecture Notes in Computer Science

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Abstract. Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reduced leakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5× higher area than the filter designed using our proposed method.

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Section: Minimum Energy Point Analysis Of Addersmentioning

confidence: 99%

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

Lecture Notes in Computer Science

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“…Thus, circuits need to be checked for failure rates while operating at extremely low voltages. In this paper the static noise margin (SNM) failure rates of the gates are extracted from 5k-point Monte Carlo analysis, which follows the methodology in [7]. It is found that the supply voltage value which realizes operation with less than 0.001 failure rate for a 65 nm process is 0.25V and this value is taken as the minimum reliable operating voltage (ROV).…”

Section: Sub-v T Operation Modementioning

confidence: 99%

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding

Rodrigues

Akgun

Acharya

et al. 2010

Lecture Notes in Computer Science

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Abstract. This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency in the sub-threshold (sub-VT ) domain. The design is synthesized in 65 nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Due to folding, energy efficiency of the circuit is increased by 14.4 % in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.

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“…More and more systems with low performance requirements are operated from a near/sub-threshold supply voltage in order to save power [3][4][5][6][7]. However, due to the fact that the gate voltage drive of the transistors operating in the sub-threshold domain is small, standard logic cells become more sensitive to process variations.…”

Section: Introductionmentioning

confidence: 99%

Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

Liu

Gyvez

Ashouei

2013

JLPEA

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Abstract:Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of [1,2] on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this paper, the equivalent N and P networks are derived based on the best and worst case transition times. The slack available in the best-case timing arc is reduced by using smaller transistors on that path, while the timing of the worst-case timing arc is improved by using bigger transistors. The optimization is done such that the overall area remains constant with regard to the area before optimization. Two sizing styles are applied, one is based on both transistor width and length tuning, and the other one is based on width tuning only. Compared to super-threshold libraries, at 0.3 V, the proposed libraries achieve 49% and 89% average cell timing improvement and 55% and 31% power delay product improvement at 40 nm and 90 nm respectively. From ITC (International Test Conference 99) benchmark circuit synthesis results, at 0.3 V the proposed library achieves up to 52% timing improvement and 53% power savings in the 40 nm technology node. OPEN ACCESSJ. Low Power Electron. Appl. 2013, 3 234

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Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits

Cited by 80 publications

References 11 publications

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding

Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

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