Dependable Multicore Architectures at Nanoscale 2017
DOI: 10.1007/978-3-319-54422-9_7
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Variation-Mitigation for Reliable, Dependable and Energy-Efficient Future System Design

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Cited by 1 publication
(4 citation statements)
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“…This is observable in the development of domain specific case-studies described in Section 4. [35,39,132,48,133,37,49], memory [46,47], cache [46,47], SPM [46,47], shared bus [3,7,134] Table 2: Selected research contributions classification by device abstraction level and fundamental safety technical requirement abstraction levels using different application specific and ad hoc combinations of research contributions (e.g., wind turbine [7,54,6,4,55]). For example, a cross-level approach is required to achieve the DC required by safety standards because, as the complexity continues to increase for device architectures, components and interconnections, meeting the required DC at software application level becomes a challenge if sufficient hardware diagnostic support is not provided [7,36,6].…”
Section: Discussionmentioning
confidence: 99%
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“…This is observable in the development of domain specific case-studies described in Section 4. [35,39,132,48,133,37,49], memory [46,47], cache [46,47], SPM [46,47], shared bus [3,7,134] Table 2: Selected research contributions classification by device abstraction level and fundamental safety technical requirement abstraction levels using different application specific and ad hoc combinations of research contributions (e.g., wind turbine [7,54,6,4,55]). For example, a cross-level approach is required to achieve the DC required by safety standards because, as the complexity continues to increase for device architectures, components and interconnections, meeting the required DC at software application level becomes a challenge if sufficient hardware diagnostic support is not provided [7,36,6].…”
Section: Discussionmentioning
confidence: 99%
“…• Process, Voltage and Temperature (PVT) variability: As the technology continues to shrink, manufacturing process variability introduces higher variability of transistor / gates properties with respect to design time properties [32,37,38]. Runtime variability due to PVT and aging, can also lead to transistor / gates variability but at different locations and operational lifetime points of the device [32,37]. This variability can lead to timing failure of circuits if design time margins are exceeded and therefore reduce the device reliability.…”
Section: Reliability Degradation Threatsmentioning
confidence: 99%
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