Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference

Abstract

Recurrent neural networks such as Long Short-Term Memories (LSTMs) learn temporal dependencies by keeping an internal state, making them ideal for time-series problems such as speech recognition. However, the outputto-input feedback creates distinctive memory bandwidth and scalability challenges in designing accelerators for RNNs. We present MUNTANIALA, an RNN accelerator architecture for LSTM inference with a silicon-measured energy-efficiency of 3.25 TOP/s/W and performance of 30.53 GOP/s in UMC 65nm technology. The scalable design of MUNTANIALA allows running large RNN models by combining multiple tiles in a systolic array. We keep all parameters stationary on every die in the array, drastically reducing the I/O communication to only loading new features and sharing partial results with other dies. For quantifying the overall system power, including I/O power, we built VAU DA MUNTANIALAS, to the best of our knowledge, the first demonstration of a systolic multi-chip-on-PCB array of RNN accelerator. Our multi-die prototype performs LSTM inference with 192 hidden states in 330µs with a total system power of 9.0mW at 10MHz consuming 2.95µJ. Targeting the 8/16-bit quantization implemented in MUNTANIALA, we show a phoneme error rate (PER) drop of approximately 3% with respect to floating-point (FP) on a 3L-384NH-123NI LSTM network on the TIMIT dataset.