Vault

Abstract

Intel's SGX o ers state-of-the-art security features, including con dentiality, integrity, and authentication (CIA) when accessing sensitive pages in memory. Sensitive pages are placed in an Enclave Page Cache (EPC) within the physical memory before they can be accessed by the processor. To control the overheads imposed by CIA guarantees, the EPC operates with a limited capacity (currently 128 MB). Because of this limited EPC size, sensitive pages must be frequently swapped between EPC and non-EPC regions in memory. A page swap is expensive (about 40K cycles) because it requires an OS system call, page copying, updates to integrity trees and metadata, etc. Our analysis shows that the paging overhead can slow the system on average by 5×, and other studies have reported even higher slowdowns for memory-intensive workloads. The paging overhead can be reduced by growing the size of the EPC to match the size of physical memory, while allowing the EPC to also accommodate non-sensitive pages. However, at least two important problems must be addressed to enable this growth in EPC: (i) the depth of the integrity tree and its cacheability must be improved to keep memory bandwidth overheads in check, (ii) the space overheads of integrity veri cation (tree and MACs) must be reduced. We achieve both goals by introducing a variable arity unied tree (VAULT) organization that is more compact and has lower depth. We further reduce the space overheads with techniques that combine MAC sharing and compression. With simulations, we show that the combination of our techniques can address most ine ciencies in SGX memory access and improve overall performance by 3.7×, relative to an SGX baseline, while incurring a memory capacity overhead of only 4.7%.

SECRET-GWAS: Confidential Computing for Population-Scale GWAS

“…In all our experiments for SECRET-GWAS, except for the EPC sensitivity test in Figure 3c, we did not trigger EPC paging. Recent work shows that increasing the scalability of the EPC is possible [35,36], and Intel has developed new approaches to increase EPC memory in SGX [28] that have recently been added to Azure's cloud offerings. Therefore, we believe that GWAS will be able to support even larger datasets with several million patients as the pace of EPC technology improves.…”

“…SGX, for instance, only provides 128-256 MB of EPC [28]. If an application's working data set size exceeds EPC size, then it triggers EPC paging -an expensive process where encrypted pages are moved back and forth between non-enclave and enclave memory, slowing down programs by 5x on average [35]. Datasets used in population-scale GWAS can be several GBs, which do not directly fit within the EPC.…”

LightBox

“…Therefore, it may not suit the performancesensitive middlebox applications. To help grow EPC in the future, a recent study proposes to refine the underlying data structure for integrity checking [84]. Whether a large EPC can overcome SGX's current performance issue without enlarging the attack surface remains an open problem.…”

Gleeok: A Family of Low-Latency PRFs and its Applications to Authenticated Encryption

“…A typical memory encryption scheme (as MEE) consists of MACs/hash functions and Authenticated Encryptions (AEs) composed in a tree for providing replay protection in addition to confidentiality and authenticity [Gue16a, HJ06, RCPS07, IMO + 22]. This type of memory encryption has been extensively studied from the system architecture viewpoint, e.g., [YEP + 06, SNR + 18a, TSB18a,Ava22]. The latency of the cryptographic core inside a memory encryption scheme directly impacts the memory read/write latency, hence it is a critical factor in determining the overall TEE performance.…”