2015 IEEE 22nd International Conference on High Performance Computing (HiPC) 2015
DOI: 10.1109/hipc.2015.54
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Vectorized Big Integer Operations for Cryptosystems on the Intel MIC Architecture

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Cited by 9 publications
(4 citation statements)
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“…Implementations targeting hardware on which efficient carry propagation mechanisms exist tend to use full-radix representations. Examples include general-purpose CPUs [9,14] and GPUs [5,6], and the first generation Xeon Phi codenamed Knight's Corner (KNC) [3,15,30]. However, the parallelization strategies differ.…”
Section: Related Workmentioning
confidence: 99%
“…Implementations targeting hardware on which efficient carry propagation mechanisms exist tend to use full-radix representations. Examples include general-purpose CPUs [9,14] and GPUs [5,6], and the first generation Xeon Phi codenamed Knight's Corner (KNC) [3,15,30]. However, the parallelization strategies differ.…”
Section: Related Workmentioning
confidence: 99%
“…Let p and q be two primes such that p = 2q + 1. Since the computational cost of some cryptographic operations such as modular multiplication, hash function or inverse is relatively small after being optimized by various technologies [34], we consider only the computationally expensive bilinear pairing and exponentiation operations in Table 1. We use the symbol P to denote one paring operation.…”
Section: Comparisonmentioning
confidence: 99%
“…The use of vector instructions for cryptographic algorithm optimization, however, is quite common. Chang et al presented an optimized implementation of the RSA algorithm, which achieved speedups of 4.3 to 5.9 times using the AVX‐512 instruction set, and Hamburg presented an implementation of elliptic‐curve cryptography using SSE and AVX instructions. Considering the code‐based cryptography field, specifically, there are also some optimization works using vector instructions.…”
Section: Related Workmentioning
confidence: 99%