2020
DOI: 10.1007/978-981-15-8767-2_25
|View full text |Cite
|
Sign up to set email alerts
|

VeNNus: An Artificial Intelligence Accelerator Based on RISC-V Architecture

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
4

Relationship

1
3

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 14 publications
0
2
0
Order By: Relevance
“…A detailed analysis of the implementation of the CNN model in TPU and GPU is done on different benchmark applications ( Ravikumar et al, 2022 ). The hardware accelerators efficiently process many machine learning algorithms in a single-node, multimode, and cloud environments ( Harini & Ravikumar, 2021 ; Harini, Ravikumar & Garg, 2021 ; Harini, Ravikumar & Keshwani, 2022 ).…”
Section: Related Workmentioning
confidence: 99%
“…A detailed analysis of the implementation of the CNN model in TPU and GPU is done on different benchmark applications ( Ravikumar et al, 2022 ). The hardware accelerators efficiently process many machine learning algorithms in a single-node, multimode, and cloud environments ( Harini & Ravikumar, 2021 ; Harini, Ravikumar & Garg, 2021 ; Harini, Ravikumar & Keshwani, 2022 ).…”
Section: Related Workmentioning
confidence: 99%
“…Since the bulk of training time has been spent on data transmission, this behavior drastically limits the advantage that may be gained via parallel training. Adopting high-performance hardware accelerators simply reduces the overhead associated with computing while keeping the overhead associated with communication unaltered [ [8] , [9] , [10] ]. This results in a more significant proportion of time being spent on communication.…”
Section: Introductionmentioning
confidence: 99%