Verification Approach of Metropolis Design Framework for Embedded Systems

Chen, Xi; Hsieh, Harry; Balarin, Felice

doi:10.1007/s10766-005-0002-x

Cited by 10 publications

(10 citation statements)

References 13 publications

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“…In most cases, these frameworks are based on the correct-by-construction paradigm and provide a formal support for the whole design process. Metropolis [CHB06] for the Metropolis MetaModel (MMM), SCADE [Ber07], and Ptolemy [EJL + 03] are three examples for these frameworks. All of these approaches focus on system-level design and verification and thus are not applicable for the stepwise refinement process down to register transfer level as used in the HW/SW codesign flow.…”

Section: Verification Frameworkmentioning

confidence: 99%

Model Checking Memory-Related Properties of Hardware/Software Co-designs

Pockrandt

Herber

Klös

et al. 2013

IFIP Advances in Information and Communication Technology

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Hardware/software codesign enables the integrated development of hardware and software in a single design language. In combination with transaction level modeling, it can be used to efficiently model complex systems on different levels of abstraction. As such systems are often used in safety-critical applications, the correctness is crucial to prevent high financial losses or casualties. Especially memory-related errors can cause severe problems as they either result in deadlocks, runtime-errors or undefined system behavior. Although HW/SW codesign usually provides means for testing and simulation during the whole development process, these techniques are incomplete and can never ensure the absence of errors. In contrast, formal verification techniques like model checking can be used to guarantee the correctness of a design. Although there exist several approaches for the formal verification of HW/SW codesigns, memory-related constructs and operations are only insufficiently considered.In this thesis, we present an approach for model checking of memoryrelated properties on digital HW/SW systems. To this end, we focus on the system level description language SystemC, the de facto standard for HW/SW codesign. To support transaction level modeling, we additionally take the widely used SystemC transaction level modeling standard (TLM) into account. The main idea of our approach is to provide a formal semantics for the most relevant parts of the TLM standard and a formal memory model, which captures all relevant memory-related constructs and operations. We combine these with an already existing formalization of the basic SystemC constructs and provide transformation rules to enable the fully automatic transformation of SystemC/TLM designs into semantically equivalent Uppaal timed automata models. On the resulting model, we use the Uppaal model checker to verify important properties, including memory-related properties, timing, liveness and safety properties. To ease this verification, we automatically generate a set of verification properties, which can be used to ensure the absence of many common errors in a given design. This includes memory-related errors like null pointer accesses and array out of bounds accesses on a given design as well as the absence of assertion violations.If a property is violated, the Uppaal model checker generates a counterexample. As our formal semantics for SystemC/TLM is structure-preserving, this counterexample can easily be transferred back to the SystemC/TLM code manually and thereby allows for the localization of detected errors. To enhance the applicability of our approach for complex designs, we provide a set of optimization techniques. These are used to reduce the semantic state space and, thus, yield a better verification performance.We have implemented our transformation and our optimization techniques in a toolchain, which can be applied to SystemC/TLM designs fully automatically. We demonstrate both, the verification performance and the errordetection capabilities of ...

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Section: Verification Frameworkmentioning

confidence: 99%

Model Checking Memory-Related Properties of Hardware/Software Co-designs

Pockrandt

Herber

Klös

et al. 2013

IFIP Advances in Information and Communication Technology

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“…The problem of integrating formal verification into the design of DSMLs has been widely addressed by the MDE community. In order to tackle property-based verification problem, authors of [20] present the Metropolis design framework for embedded systems.…”

Section: Related Workmentioning

confidence: 99%

Formal Verification Integration Approach for DSML

Zalila

Crégut

Pantel

2013

Lecture Notes in Computer Science

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The application of formal methods (especially, model checking and static analysis techniques) for the verification of safety critical embedded systems has produced very good results and raised the interest of system designers up to the application of these technologies in real size projects. However, these methods usually rely on specific verification oriented formal languages that most designers do not master. It is thus mandatory to embed the associated tools in automated verification toolchains that allow designers to rely on their usual domain-specific modeling languages (DSMLs) while enjoying the benefits of these powerful methods. More precisely, we propose a language to formally express system requirements and interpret verification results so that system designers (DSML end-users) avoid the burden of learning some formal verification technologies. Formal verification is achieved through translational semantics. This work is based on a metamodeling pattern for executable DSML that favors the definition of generative tools and thus eases the integration of tools for new DSMLs.

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“…Some of them, like the Ptolemy tool [2], don't support a layered abstraction level design approach and use a single specification including both functional behavior and architecture models. Others support the platform-based design approach (like Metropolis [3]) or the top-down design methodology (like SpecC [4]). However, it is demonstrated that the Y-chart layer's based approach, which is followed by several recent works, became nowadays the most popular and used for designing heterogeneous multiprocessors embedded systems.…”

Section: System-level Exploration Tools Comparative Synthesismentioning

confidence: 99%

System-Level Performance Evaluation of Very High Complexity Media Applications : A H264/AVC Encoder Case Study

Zrida¹,

Jemai²,

Ammari³

et al. 2011

IJCNS

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Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application; a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms

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Verification Approach of Metropolis Design Framework for Embedded Systems

Cited by 10 publications

References 13 publications

Model Checking Memory-Related Properties of Hardware/Software Co-designs

Model Checking Memory-Related Properties of Hardware/Software Co-designs

Formal Verification Integration Approach for DSML

System-Level Performance Evaluation of Very High Complexity Media Applications : A H264/AVC Encoder Case Study

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