Verification of Embedded Memory Systems using Efficient Memory Modeling

Ganai, Malay K.; Gupta, Aarti; Ashar, Pranav

doi:10.1109/date.2005.325

Cited by 14 publications

(15 citation statements)

References 24 publications

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“…In addition to our own memory model, we implement the memory model in [9] and extend it to handle arbitrary initial memory configurations in a design debugging context. We also include results for the explicit memory representation which models memory as an array of flip-flops.…”

Section: Methodsmentioning

confidence: 99%

“…This information is easily obtained by a standard simulator. It should be noted that using similar types of constraints as described above, the crossbar model in [9] can be extended to deal with initial memory configurations as well. …”

Section: A Modeling Initial Memory Configurationsmentioning

confidence: 99%

“…In this work, we refer to the SAT-based memory model of [9] as the crossbar model. The crossbar model removes the memory array but maintains the control and interface signals.…”

Section: Existing Memory Modelsmentioning

confidence: 99%

“…A memory model for BMC is described in [9]. In this work, we refer to the SAT-based memory model of [9] as the crossbar model.…”

Section: Existing Memory Modelsmentioning

confidence: 99%

“…However, [8] does not account for memories explicitly. A memory model is proposed by [9] for Bounded Model Checking (BMC). The technique eliminates memory arrays but keeps the memory interface and the control logic.…”

Section: Introductionmentioning

confidence: 99%

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A succinct memory model for automated design debugging

Keng¹,

Mangassarian²,

Veneris³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-In today's complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to the difficulty of the problem by exponentially increasing the statespace of the design. In this work, a novel memory model for design debugging is presented. It models memory succinctly by avoiding an explicit representation for each memory bit. The method uses the simulation of the erroneous design to guide the debugging process. This results in a parameterizable formal encoding that grows linearly with the erroneous trace length, significantly reducing the memory requirements of the debugging problem. In addition, the proposed model is extended to handle an arbitrary initial memory configuration, as well as non-cycle accurate output traces where only a final expected memory state is available for comparison. Experiments on industrial designs show a 96% average reduction in memory usage along with a noticeable performance improvement compared to previous work.

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Section: Methodsmentioning

confidence: 99%

Section: A Modeling Initial Memory Configurationsmentioning

confidence: 99%

“…In this work, we refer to the SAT-based memory model of [9] as the crossbar model. The crossbar model removes the memory array but maintains the control and interface signals.…”

Section: Existing Memory Modelsmentioning

confidence: 99%

“…A memory model for BMC is described in [9]. In this work, we refer to the SAT-based memory model of [9] as the crossbar model.…”

Section: Existing Memory Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A succinct memory model for automated design debugging

Keng¹,

Mangassarian²,

Veneris³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

View full text Add to dashboard Cite

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DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems

Ganai¹,

Gupta²,

Ashar³

2005

Tools and Algorithms for the Construction and Analysis of Systems

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Abstract. We present a SAT-based model checking platform (DiVer) based on robust and scalable algorithms that are tightly integrated for verifying large scale industry designs. DiVer houses various SAT-based engines each targeting capacity and performance issues inherent in verifying large designs. The engines with their respective roles are as follows: Bounded Model Checking (BMC) and Distributed BMC over a network of workstations for falsification, Proof-based Iterative Abstraction (PBIA) for model reduction, SAT-based Unbounded Model Checking and Induction for proofs, Efficient Memory Modeling (EMM) and its combination with PBIA in BMC for verifying embedded memory systems with multiple memories (with multiple ports and arbitrary initial state). Using several industrial case studies, we describe the interplay of these engines highlighting their contribution at each step of verification. DiVer has matured over 3 years and is being used extensively in several industry settings. Due to an efficient and flexible infrastructure, it provides a very productive verification environment for research and development.

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