Verification of fixed-point digital controllers using direct and delta forms realizations

Bessa, Iury; Ismail, Hussama; Cordeiro, Lucas C.; Filho, João Edgar Chaves

doi:10.1007/s10617-016-9173-5

Cited by 25 publications

(52 citation statements)

References 82 publications

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“…In order to tackle such problem, this paper proposes a verification methodology based on bounded model checking (BMC) techniques [11], which verifies properties on statespace digital controllers, by means of a verification tool named as Digital-Systems Verifier (DSVerifier). It is worth noting that this paper extends a previous work [7,18,2,13,6]. In particular, the major improvement of the DSVerifier version described here relies on the support for state-space models, which allows a better insight about the internal system behavior, enables the verification of new properties (e.g., controllability and observability), and considers initial conditions for system analysis [14].…”

Section: Motivationmentioning

confidence: 91%

“…In contrast, Alur et al [3,4] proposed the prior automated verification approaches, regarding model checking, which inspired the development of other verifiers for cyber-physical systems and hybrid automata (e.g., Maellan [32], Open-Kronos [33], and UPPAAL [5]). Nonetheless, differently from the work presented here, such approaches do not tackle system robustness related to implementation aspects [7,18,2].…”

Section: Background and Related Workmentioning

confidence: 95%

“…Such models can be translated into algorithms and implemented in several kinds of microprocessors (e.g., field programmable gate arrays (FPGA) devices [27] and digital signal processors [24]). Importantly, each one of these platforms can manipulate and represent numbers using different formats and arithmetics (e.g., number of bits, fixedor floating-point arithmetic), which can directly affect the performance and precision of the digital-control system [7].…”

Section: Motivationmentioning

confidence: 99%

See 2 more Smart Citations

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Monteiro

2016

Proceedings of the 2016 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering

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The extensive use of digital controllers demands a growing effort to prevent design errors that appear due to finiteword length (FWL) effects. However, there is still a gap, regarding verification tools and methodologies to check implementation aspects of control systems. Thus, the present paper describes an approach, which employs bounded model checking (BMC) techniques, to verify fixed-point digital controllers represented by state-space equations. The experimental results demonstrate the sensitivity of such systems to FWL effects and the effectiveness of the proposed approach to detect them. To the best of my knowledge, this is the first contribution tackling formal verification through BMC of fixed-point state-space digital controllers.

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Section: Motivationmentioning

confidence: 91%

Section: Background and Related Workmentioning

confidence: 95%

Section: Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Monteiro

2016

Proceedings of the 2016 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering

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“…Indeed, digital filters and controllers [31,43,44] were tackled, in order to specify system-level properties of those systems, using linear-time temporal logic [45]. In particular, a specific UAV application was tackled, with the goal to verify its attitude controllers [46]. In general, however, there is still a lack of studies to verify systemlevel properties related to embedded systems; emphasis should be given to micro-grids [2] and cyber-physical systems [4], which require high-dependability requirements for computation, control, and communication.…”

Section: Current Achievements and Future Trendsmentioning

confidence: 99%

SMT-Based Context-Bounded Model Checking for Embedded Systems

Cordeiro

Filho

2016

SIGSOFT Softw. Eng. Notes

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The dependency on the correct functioning of embedded systems is rapidly growing, mainly due to their wide range of applications, such as micro-grids, automotive device control (e.g., airbag control), health care, surveillance, mobile devices, and consumer electronics. Their structures are becoming more and more complex and now require multi-core processors with scalable shared memory, in order to meet increasing computational power demands. As a consequence, reliability of embedded (distributed) software becomes a key issue during system development, which must be carefully addressed and assured. Normally, state-of-the-art verification methodologies for embedded systems generate test vectors (with constraints) and use assertion-based verification and highlevel processor models, during simulation; however, other additional challenges have been raised: the need for meeting time and energy constraints, handling concurrent software, dealing with platform restrictions, evaluating implementation-structure choices, and supporting new software architectures and legacy designs (usually written in low-level languages). The present paper discusses challenges, problems, and recent advances to ensure correctness and timeliness regarding embedded systems. Reliability issues, in the development of micro-grids and cyber-physical systems, are then considered, as a prominent (bounded) model checking application.

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“…Hardware choice, structure representations (e.g., direct forms), and implementation features (e.g., number of integer and fractional bits, in fixed-point arithmetic) can heavily influence a given digital-system's precision and performance [2]. Additionally, such implementations are particularly susceptible to finite word-length (FWL) effects (e.g., overflows, limit cycles, and poles and zeros sensitivity), which have the potential to reduce the associated reliability and efficiency.…”

Section: Introductionmentioning

confidence: 99%

Verifying digital systems with MATLAB

Chaves

Bessa

Cordeiro

et al. 2017

Proceedings of the 26th ACM SIGSOFT International Symposium on Software Testing and Analysis

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A MATLAB toolbox is presented, with the goal of checking occurrences of design errors typically found in fixed-point digital systems, considering finite word-length effects. In particular, the present toolbox works as a front-end to a recently introduced verification tool, known as Digital-System Verifier, and checks overflow, limit cycle, quantization, stability, and minimum phase errors, in digital systems represented by transfer-function and state-space equations. It provides a command-line version, with simplified access to specific functions, and a graphical-user interface, which was developed as a MATLAB application. The resulting toolbox is important for the verification community, since it shows the applicability of verification to real-world systems.

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Verification of fixed-point digital controllers using direct and delta forms realizations

Cited by 25 publications

References 82 publications

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

SMT-Based Context-Bounded Model Checking for Embedded Systems

Verifying digital systems with MATLAB

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