Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

Pandey, Jyoti; Asati, Abhijit R.; Shenoy, Meetha V.; Sikka, Prateek

doi:10.1109/gcat59970.2023.10353312

Cited by 1 publication

(1 citation statement)

References 25 publications

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“…While delineating design behaviours at high abstraction levels, HLS is swiftly gathering traction among designers in search of a method to guarantee continuous verification throughout the design cycle [15]. Illustrative software for HLS comprises Vivado HLS [16] and MATLAB HDL Coder [17]. Moreover, an extensive array of open-source alternatives can be found.…”

Section: High-level Synthesis Based On Hdl Codermentioning

confidence: 99%

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

Slimane

2024

IJITS

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Field Programmable Gate Arrays (FPGAs) have garnered significant attention in the development and enhancement of target identification algorithms that employ YOLOv2 models and FPGAs, owing to their adaptability and user-friendliness. The Simulink HDL compiler was utilized to design, simulate, and implement our proposed design. In an effort to rectify this, this paper presents a comprehensive programming and design proposal. The implementation of the YOLOv2 algorithm for real-time vehicle detection on the Xilinx® Zynq-7000 System-on-a-chip is proposed in this work. Real-time testing of the synthesised hardware revealed that it can process Full HD video at a rate of 16 frames per second. On the Xilinx Zynq-7000 SOC, the estimated dynamic power consumption is less than 90 mW. When comparing the results of the proposed work to those of other simulations, it is observed that resource utilization is enhanced by around 204 k (75%) LUT, 305 (12%) DSP, and 224 k (41%) flip-flops at 200 MHz.

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Section: High-level Synthesis Based On Hdl Codermentioning

confidence: 99%

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

Slimane

2024

IJITS

View full text Add to dashboard Cite

show abstract

Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

Cited by 1 publication

References 25 publications

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

Efficient Real time Zynq 7000 FPGA deployment of optimized YOLOv2 deep leaning model for target detection, based on HDL Coder Methodology

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