Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays

Chen, Yung-Chih; Wang, Chun-Yao; Huang, Ching-Yi

doi:10.1109/tcad.2013.2267453

“…The mapped results were verified by an SET verification tool [5]. The experimental results show that our approach saves 26% of the width compared to [7] while spending similar CPU time.…”

Section: Introductionmentioning

confidence: 97%

“…To deal with this issue, many ultra-low power devices have been explored. Since the power consumption of Single-Electron Transistors (SETs) [9], which work with only one or few electrons during switching operations, is ultra-low, SETs are considered as a promising candidate that substitutes conventional Complementary Metal-Oxide-Semiconductor (CMOS) devices for future VLSI/SoC designs [5] [15][17] [20].…”

Section: Introductionmentioning

confidence: 99%

Width minimization in the Single-Electron Transistor array synthesis

Liu

¹

,

Chiang

²

,

Huang

³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Power consumption has become one of the primary challenges to meet the Moore's law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption during operation. Prior work has proposed an automated mapping approach for SET arrays which focuses on minimizing the number of hexagons in an SET array. However, the area of an SET array is more related to the width. Consequently, in this work, we propose an approach for width minimization of the SET arrays. The experimental results show that the proposed approach saves 26% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks while spending similar CPU time.

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“…We conducted the experiments on a set of MCNC [19] and IWLS 2005 [21] benchmarks. The mapped results were verified by an SET verification tool [5]. The experimental results show that our approach saves 26% of the width compared to [7] while spending similar CPU time.…”

Section: Introductionmentioning

confidence: 97%

“…To deal with this issue, many ultra-low power devices have been explored. Since the power consumption of Single-Electron Transistors (SETs) [9], which work with only one or few electrons during switching operations, is ultra-low, SETs are considered as a promising candidate that substitutes conventional Complementary Metal-Oxide-Semiconductor (CMOS) devices for future VLSI/SoC designs [5] [15][17] [20].…”

Section: Introductionmentioning

confidence: 99%

Width minimization in the Single-Electron Transistor array synthesis

Liu

¹

,

Chiang

²

,

Huang

³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

1

0

View full text Add to dashboard Cite

Power consumption has become one of the primary challenges to meet the Moore's law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption during operation. Prior work has proposed an automated mapping approach for SET arrays which focuses on minimizing the number of hexagons in an SET array. However, the area of an SET array is more related to the width. Consequently, in this work, we propose an approach for width minimization of the SET arrays. The experimental results show that the proposed approach saves 26% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks while spending similar CPU time.

show abstract

“…The SET device means the possibility to control the place and transport of an electron based on the quantized nature of charge. The SET circuits have potential advantages of ultra-small size and ultra-low power consumption [12][13][14]. However, most of nanoelectronic circuits have been realized as a network of SET-based AND, OR and NOT gates that might be severely affected by a great circuit-depth and alternative solutions are required.…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation of Single-electron Tunneling based Nano-electronics Circuits

M.¹

2018

CAE

0

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Among various nanotechnology devices, single-electron tunneling devices are the most promising candidates to substitute the present CMOS devices. In this paper, a new single-electron threshold-logic circuit module is presented for realizing and implementing Nano-electronic circuits. The proposed module can be dedicated to implement all basic logic gates, such as OR, NOR, AND, NAND, XOR and XNOR gates, that can be integrated in various manners to design digital circuits. The simulation results demonstrate the accuracy and stability of proposed circuit module. Design capability and flexibility of this module are further evaluated through the synthesis of high-level circuits.

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Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays

Cited by 12 publications

References 17 publications

Width minimization in the Single-Electron Transistor array synthesis

Width minimization in the Single-Electron Transistor array synthesis

Width minimization in the Single-Electron Transistor array synthesis

Design and Simulation of Single-electron Tunneling based Nano-electronics Circuits

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