Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

He, Ze; Zhao, Shiwei; Liu, Tianqi; Cai, Chang; Yan, Xiaoyu; Gao, Shuai; Liu, Yuzhu; Liu, Jie

doi:10.1007/s41365-021-00979-8

Cited by 5 publications

(1 citation statement)

References 48 publications

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“…Luo等 [13] 研究了入射角对SEU和单粒子多位翻转 (multiple-cell upsets, MCU)的影响, 证明SRAM 中大倾角沿阱入射是SEU和MCU的最差取向, 粒子大倾斜角入射增大SEU反应截面, 大大降低 SEU阈值; Hsiao等 [14] 2 仿真建模目前主要有飞行实验、重离子辐射装置实验和计算机仿真实验这3种辐照效应研究方法 [15] 使得锁存单元的数据状态实现翻转再恢复 [16] . [17] , 本文共选取 7种 LET 值, 分别为10.0, 15.0, 20.0, 30.0, 37.0, 40.0, 50.0 MeV•cm 2 /mg, 设置MOS管间间距为0.8 μm, 粒子垂直轰击关态DN3或DP4漏极中心, 仿真得到DA节点的电压脉冲变化如图7所示.…”

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Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

Zhang,

Liu,

et al. 2024

Acta Phys. Sin.

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With the development of nanoscale circuit technology, the on-track error rate of digital circuits and the impact of single event upset has become more pronounced. The radiation resistance research on DICE SRAM or DICE flip-flop devices has been carried out by scholars from domestic and foreign, including 65 nm, 90 nm, and 130 nm, etc. However, scholars have never published any related articles about the 55 nm DICE latch. With the three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD, we verified the reinforcement performance of the DICE circuit, and clarified the effects of different incident conditions on DICE circuits. At the same time, we compared the anti-SEU performance of NMOS and PMOS transistors in the 55 nm process through comparative simulation experiments and quantitative analysis. The investigation shows that one of the important factors is the LET value which affecting the generation rate of electron-hole pairs. A higher LET value will extend the upset recovery time of devices and increase the peak of voltage. In addition, the difference in the charge-sharing mechanism of transistors leads to the recovery time of PMOS higher than NMOS; As the angle of incidence increases, the charge-sharing mechanism between adjacent devices are enhanced, and electron-hole pairs ionized in sensitive regions increased. Due to the difference in charge mobility, the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit. Therefore, strict tilt angle incident test evaluation is required for DICE devices before practical application; Finally, the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes, it’s found that the distance between the MOS transistors in the 55 nm process must not be less than 1.2 μm by device simulation. Relevant simulation results can provide a theoretical basis and data support for the study of the physical mechanism of SEU and reinforcement technology, then accelerate the application of memory devices in the aerospace field.

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Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

Zhang,

Liu,

et al. 2024

Acta Phys. Sin.

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Differences in MBUs induced by high-energy and medium-energy heavy ions in 28 nm FPGAs

Gao

Yang

et al. 2022

NUCL SCI TECH

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Heavy ion-induced MCUs in 28 nm SRAM-based FPGAs: upset proportions, classifications, and pattern shapes

Gao

Zhao

et al. 2022

NUCL SCI TECH

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Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

Cited by 5 publications

References 48 publications

Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

Differences in MBUs induced by high-energy and medium-energy heavy ions in 28 nm FPGAs

Heavy ion-induced MCUs in 28 nm SRAM-based FPGAs: upset proportions, classifications, and pattern shapes

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