Verification of Synchronous Elastic Processors

Srinivasan, Sudarshan K.; Sarker, Koushik; Katti, R.

doi:10.1109/les.2009.2028043

Cited by 3 publications

(4 citation statements)

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“…We use the ACL2-SMT system for verification as it can be used to reason at the term-level. Note that bit-level versions of these models were used in [7]. The models were obtained by first elasticizing a synchronous 5-stage DLX processor using the Synchronous Elastic Flow (SELF) protocol approach [2].…”

Section: Elastic Processor Modelsmentioning

confidence: 99%

“…This is achieved by first computing the reachable states of the elastic controller network. We use token-flow diagrams proposed in [7] to compute the reachable states of the system. The reachability analysis is performed by simulating how tokens flow in the elastic architecture using a form of symbolic simulation.…”

Section: Token-aware Completion Functionsmentioning

confidence: 99%

“…In previous work, we have developed an equivalence checking approach that is used to verify elastic pipelines against their synchronous parent pipelines [7].…”

Section: Introductionmentioning

confidence: 99%

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Token‐Aware Completion Functions for Elastic Processor Verification

Srinivasan

Sarker

Katti

2009

Journal of Electrical and Computer Engineering

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We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA) specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which-in the context of this problem-are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

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Section: Elastic Processor Modelsmentioning

confidence: 99%

Section: Token-aware Completion Functionsmentioning

confidence: 99%

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Token‐Aware Completion Functions for Elastic Processor Verification

Srinivasan

Sarker

Katti

2009

Journal of Electrical and Computer Engineering

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“…S.K. Srinivasan [5] designed a formal verification procedure to check the synchronous elastic pipelined processors.…”

Section: Introductionmentioning

confidence: 99%

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

Pan

Ling

2010

AMM

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The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The verification procedure is to compare the equivalence of the multiple-valued decision diagrams of two types of cone structures. Experimental results on a lot of benchmark circuits show the method presented in this paper can effectively perform the equivalence checking of circuits.

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