Verification platform research base on SystemC design

Abstract

With the development of electronics, the design of hardware becomes more and more complicated, which increase the difficulty of validation accordingly. Hardware and software design cooperatively on simulation and verification, which not only solve the problems of Hardware Model on higher levels, but it also has become a popular design method. The effectiveness of programming languages on system-level and service-level is remarkable. As a result, the paper introduces the practicability of SystemC on Hardware Model, and makes great play with the function and method of verification. At last, full adder Hardware Model is established successfully.