Verifying a Simple Pipelined Microprocessor Using Maude

Harman, Neal A.

doi:10.1007/3-540-45645-7_7

Cited by 21 publications

(11 citation statements)

References 27 publications

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“…The earliest work I know on hardware specification and verification using Maude is by Harman [228,229]. Subsequent work has focused mostly on extending the rewriting logic semantics project from the level of programming languages to that of hardware description languages (HDLs).…”

Section: Hardware Specification and Verificationmentioning

confidence: 99%

Twenty years of rewriting logic

Meseguer

2012

The Journal of Logic and Algebraic Programming

165

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Rewriting logic is a simple computational logic that can naturally express both concurrent computation and logical deduction with great generality. This paper provides a gentle, intuitive introduction to its main ideas, as well as a survey of the work that many researchers have carried out over the last twenty years in advancing: (i) its foundations; (ii) its semantic framework and logical framework uses; (iii) its language implementations and its formal tools; and (iv) its many applications to automated deduction, software and hardware specification and verification, security, real-time and cyber-physical systems, probabilistic systems, bioinformatics and chemical systems.

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Section: Hardware Specification and Verificationmentioning

confidence: 99%

Twenty years of rewriting logic

Meseguer

2012

The Journal of Logic and Algebraic Programming

165

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“…An alternative semantics for digital circuits is described in [10], where instead of a synchronizing rewrite rule, each node value is tagged with the cycle number for which the node takes on the calculated value. In that scheme, it is not necessary to have any rewrite rules, but for use with the Maude model checker, it was cleaner and more useful to specify synchronization as explained above.…”

Section: Op [___] : Nodetype Identifier Value -> Nodevaluementioning

confidence: 99%

A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis

Katelman

Meseguer

2007

Electronic Notes in Theoretical Computer Science

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We present a rewriting logic semantics in Maude of the ABEL hardware description language. Based on this semantics, and on Maude's underlying LTL model checker, we propose a scalable formal analysis framework and tool for hardware/software co-design. The analysis method is based on trace checking of finite system behaviors against LTL temporal logic formulas. The formal properties of the hardware, the embedded software, and the interactions between both can all be analyzed this way. We present two case studies illustrating our method and tool.

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“…Various symbolic tools required long CPU time when formally verifying a pipelined DLX Ritter et al, 1999), or ran out of memory (Isles et al, 1998). Custom-tailored, manually defined rewriting rules were used to formally verify a five-stage DLX (Levitt and Olukotun, 1997), and similar four-stage processors (Harman, 2001;Lis, 2000;Matthews and Launchbury, 1999), but would require modifications to work on designs described in a different coding style and significant extensions to scale for dual-issue superscalar processors. Other researchers proved only few properties of a pipelined DLX (Ivanov, 2002;Ramesh and Bhaduri, 1999), or did not present completeness argument (Mishra and Dutt, 2002)--that the properties proved will ensure correctness under all possible scenarios.…”

Section: Related Workmentioning

confidence: 99%

TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories

Velev¹,

Bryant²

2005

IJES

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We present a tool flow for high-level design and formal verification of embedded processors. The tool flow consists of the term-level symbolic simulator TLSim, the decision procedure EVC (Equality Validity Checker) for the logic of Equality with Uninterpreted Functions and Memories (EUFM), and any SAT solver. TLSim accepts high-level models of a pipelined implementation processor and its non-pipelined specification, as well as a command file indicating how to simulate them symbolically, and produces an EUFM formula for the correctness of the implementation. EVC exploits the property of Positive Equality and other optimisations in order to translate the EUFM formula to an equivalent Boolean formula that can be solved with any SAT procedure. An earlier version of our tool flow was used to formally verify a model of the M • CORE processor at Motorola, and detected bugs.Keywords: design automation; hardware design languages; logic; microprocessors; simulation; symbolic manipulation.Reference to this paper should be made as follows: Velev, M.N. and Bryant, R.E. (2005) 'TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories', Int.

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Verifying a Simple Pipelined Microprocessor Using Maude

Cited by 21 publications

References 27 publications

Twenty years of rewriting logic

Twenty years of rewriting logic

A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis

TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories

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