Verifying equivalence of memories using a first order logic theorem prover

Abstract

We propose a new method for equivalence checking of RTL and schematic descriptions of memories using translation into first-order logic. Our method is based on a powerful abstraction of memories and address decoders within them. We propose two ways of axiomatizing some of the bit-vector operations, decoders, and memories. The first axiomatization uses an algebra of operations on bit-vectors. The second axiomatization considers a bit-vector as a unary relation and memory as a relation of larger arity. For some designs, including real-life designs, the second axiomatization results in a first-order problem falling into a known decidable fragment of first-order logic and suitable for solving by modern first-order provers. Equivalence of real-life memories can be verified in seconds with our approach.

bv2epr: A Tool for Polynomially Translating Quantifier-Free Bit-Vector Formulas into EPR

“…bv2epr translates QF BV formulas into Effectively Propositional Logic (EPR), which is NExpTimecomplete [4], by using a new (polynomial) reduction. This is in contrast to existing translations in [5,6], which produce exponential EPR formulas in general, as we will point out in Sect. 2.1.…”

“…Previous translations from QF BV into EPR also apply bit-blasting on certain operators and introduce exponentially many constants resp. constraints in the general case [5,6]. In contrast to this, the Translator used in bv2epr always produces EPR formulas of polynomial size.…”

“…In [5], encodings of hardware verification problems with bit-vectors into firstorder logic are proposed. In particular, an encoding into EPR is given and called the relational encoding [6], since bit-vectors are modeled as unary predicates.…”

“…All the arithmetic operators are assumed to be synthesized/bit-blasted in the verification front-end [6], potentially leading to an exponential blowup already before the actual encoding. In [5], an abstraction of shifts is proposed, which is, however, basically the same as bit-blasting. Consequently, the relational encoding is exponential in general, in constrast with our translation in Sect.…”

Inst-Gen – A Modular Approach to Instantiation-Based Automated Reasoning

“…The EPR is a clausal fragment of first-order logic where the signature is restricted to contain only predicate symbols and constants. This fragment is decidable and recently has been shown to have a number of applications ranging from hardware verification [17,28,40] to ontological reasoning [49], see [4] for more examples. Let us show that DSInst-Gen is a decision procedure for the EPR fragment.…”