Verifying Pipelines with BAT

Btor

“…Prominent examples of such formats are, first of all, the DIMACS format [15] for SAT solvers, the TPTP format [22] for automatic theorem provers, the BAT format [18] for machine descriptions and LTL specifications, the Spear Format (SF) [3] for bit-vectors, and the CVC [1] and SMT-LIB format [20] for SMT solvers. More recently, the second author proposed a standard format for hardware model checking, called AIGER [5], which is used in the hardware model checking competition (HWMCC).…”

“…In the first clock cycle indicated by register flag (lines 5 and 21), registers start and end are set to values start in and end in (lines 9-12 and 13-15), which represent user inputs, and remain constant afterwards. Value zero is written to memory (lines 22-27) at location p, which is first set to start and then incremented (lines[16][17][18][19][20] until end. Bad states (lines 28-40) represent that it is possible to read a non-zero value from a location between start and end after clearing memory has finished.…”