Versatile architecture-level fault injection framework for reliability evaluation: A first report

Abstract

Forthcoming technologies hold the promise of a significant increase in integration density, performance and functionality. However, a dramatic change in microprocessor's reliability is also expected. Developing mechanisms for early and accurate reliability estimation will save significant design effort, resources and consequently will positively impact product's timeto-market (TTM). In this paper, we propose a versatile architecture-level fault injection framework, built on top of a state-of-the-art x86 microprocessor simulator, for thorough and fast characterization of a wide range of hardware components with respect to various fault models.

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

“…MAFin is the CLERECO fault injector framework created on top of the MARSSx86 micro-architecture level simulator [54]. MARSSx86 [55] is a full system simulator built on top of PTLsim simulator [56] and incorporating the QEMU emulator.…”

“…The fault injection infrastructure provides users with the capability of tracing the propagation of a fault in a hardware structure at the micro-architectural level, till its manifestation at the ISA, operating system or application level [54]. Fig.…”

Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level

“…A major missing part of the microprocessor models in simulators is that of the data/instruction arrays in caches, improving simulation time but rendering reliability studies through fault injection impossible. Thus, extensions in these structures are inevitable to make fault injection experiments feasible [6] [7].…”

“…are of prevalent importance since occupy very large parts of the chip's silicon estate and largely determine the overall microprocessor reliability. Several microprocessor reliability studies are used for early reliability assessments based on ACE (Architecturally Correct Execution) analysis [8] [9] [10] [14], probabilistic models [11] [12] or fault injection [6] [7] [13] [14] [15]. Probabilistic models as well as ACE analysis are undoubtedly faster than fault injection, but they overestimate the vulnerability of microprocessor structures by several times [14] [16].…”

“…Probabilistic models as well as ACE analysis are undoubtedly faster than fault injection, but they overestimate the vulnerability of microprocessor structures by several times [14] [16]. On the other hand, fault injection on top of microarchitectural simulators resembles much closer the actual behavior of hardware and software in the presence of faults [6] [14]. Statistically significant fault injection campaigns on such infrastructures deliver very accurate reports on the faulty behavior of hardware components [17] at the expense of larger simulation times.…”