Versatile CMOS-MEMS integrated piezoelectric platform

Tsai, J. M.; Daneman, M.; Boser, Bernhard E.; Horsley, David A.; Rais‐Zadeh, Mina; Tang, Hao-Yen; Lu, Yahai; Rozen, Ofer; Liu, F.; Lim, M. H.; Assaderaghi, F.

doi:10.1109/transducers.2015.7181409

Cited by 38 publications

(15 citation statements)

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“…Each PMUT is a piezoelectric unimorph composed of 1-μm-thick AlN sandwiched between 300 nm Al and 200 nm Mo electrodes on a single-crystal silicon layer with 1.6 μm nominal thickness (Figure 1b). Al-Ge eutectic bonds on SiO 2 standoffs provide the mechanical anchor and electrical contact to the PMUT 9 . The deformation of a PMUT with an external electrical field applied to the AlN is shown in Figure 1c.…”

Section: Methodsmentioning

confidence: 99%

“…8), making them unsuitable for electrical interconnect to individual MUTs in a 500 DPI array, where the pitch between MUTs is 50 μm or less. Here, a MEMS-CMOS eutectic wafer-bonding process used for high-volume manufacturing of inertial sensors was adapted to produce PMUT arrays, enabling each PMUT to be directly bonded to a dedicated CMOS receive amplifier to minimize electrical parasitics 9 . In an earlier fingerprint sensor designed with this technology, a 17% fillfactor PMUT array achieved 14 kPa peak-to-peak pressure output, 0.6 μV Pa − 1 sensitivity and 200 μm image resolution 6 .…”

Section: Introductionmentioning

confidence: 99%

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Monolithic ultrasound fingerprint sensor

et al. 2017

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This paper presents a 591 × 438-DPI ultrasonic fingerprint sensor. The sensor is based on a piezoelectric micromachined ultrasonic transducer (PMUT) array that is bonded at wafer-level to complementary metal oxide semiconductor (CMOS) signal processing electronics to produce a pulse-echo ultrasonic imager on a chip. To meet the 500-DPI standard for consumer fingerprint sensors, the PMUT pitch was reduced by approximately a factor of two relative to an earlier design. We conducted a systematic design study of the individual PMUT and array to achieve this scaling while maintaining a high fill-factor. The resulting 110 × 56-PMUT array, composed of 30 × 43-μm 2 rectangular PMUTs, achieved a 51.7% fill-factor, three times greater than that of the previous design. Together with the custom CMOS ASIC, the sensor achieves 2 mV kPa − 1 sensitivity, 15 kPa pressure output, 75 μm lateral resolution, and 150 μm axial resolution in a 4.6 mm × 3.2 mm image. To the best of our knowledge, we have demonstrated the first MEMS ultrasonic fingerprint sensor capable of imaging epidermis and sub-surface layer fingerprints. INTRODUCTIONFingerprint sensors capture an electronic image of a human fingerprint through various physical mechanisms, including optical, capacitive, pressure and acoustic mechanisms. Capacitive fingerprint sensors are the standard for identity authentication in numerous applications because of their performance and low cost; the latter is due to the fact that these sensors can be manufactured in a standard integrated circuit manufacturing process. Ultrasonic fingerprint sensors have many advantages over capacitive sensors, including being insensitive to contamination and moisture on the finger. In addition, ultrasonic waves used in pulse-echo imaging can penetrate the finger's epidermis, collecting images of sub-surface features. However, ultrasonic fingerprint sensors previously provided a low resolution or were too difficult to manufacture. With the rapid development of microelectromechanical systems (MEMS) technology, micromachined ultrasonic transducers (MUTs) based on capacitive (CMUT) and piezoelectric (PMUT) transduction have been demonstrated with significantly reduced device sizes for high-resolution applications, low power consumption and better acoustic impedance matching to the medium

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Monolithic ultrasound fingerprint sensor

et al. 2017

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“…[84] and [77] for motion sensing, in Refs. [85] and [86] for ultrasound sensing, and in Ref. [87] for piezoelectric energy harvesting.…”

Section: Mems Integrationmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…A good replacement to the series inductor used for voltage boosting, Section II, is a high Q 2-port piezoelectric laterally-vibrating MEMS resonator [7,8]; which can be integrated with a CMOS process [6]. This device is based on a piezoelectric plate sandwiched between two patterned metal layers that are employed to create an electric field across the thickness of the piezoelectric film (H), Fig.…”

Section: High-q Mems Resonatormentioning

confidence: 99%

“…The increase in voltage to the rectifier results in a larger steady-state DC voltage being sensed by a fully differential comparator in negative feedback. The high-Q piezoelectric resonators can be fabricated in an AlN MEMS process, AlN plate sandwiched between Mo (bottom) and Al (top), that is eutecticly bonded to a 0.18 µm CMOS die [6]. This monolithic structure can then be wire bonded to the 0.13 µm WuRx implemented in this work.…”

Section: Introductionmentioning

confidence: 99%

A 170nW CMOS wake-up receiver with −60 dBm sensitivity using AlN high-Q piezoelectric resonators

Block

Jiang

Harris

et al. 2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-A new wake-up receiver (WuRx) designed in 0.13 µm CMOS process is hybrid-integrated with a microelectromechanical system (MEMS) RF resonator. While only consuming 166 nW of power (18.8 nW for the comparator and 147 nW for periphery), the WuRx is capable of detecting RF signals as weak as -60 dBm. In order to achieve this sensitivity, a passive voltage-boosting network comprised of a high quality factor (high-Q) piezoelectric MEMS resonator is utilized, in place of an inductor, to amplify the received voltages applied to a CMOS rectifier. The output of the rectifier is then applied to a low-power comparator used to set a logical bit that indicates when an RF signal has been detected. The trade-offs in designing the voltage boosting network are explained and an equation for the optimum number of rectifier stages is derived.

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Versatile CMOS-MEMS integrated piezoelectric platform

Cited by 38 publications

References 0 publications

Monolithic ultrasound fingerprint sensor

Monolithic ultrasound fingerprint sensor

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

A 170nW CMOS wake-up receiver with −60 dBm sensitivity using AlN high-Q piezoelectric resonators

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