2022 IEEE International Reliability Physics Symposium (IRPS) 2022
DOI: 10.1109/irps48227.2022.9764569
|View full text |Cite
|
Sign up to set email alerts
|

Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
7
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
5
4

Relationship

0
9

Authors

Journals

citations
Cited by 12 publications
(7 citation statements)
references
References 36 publications
0
7
0
Order By: Relevance
“…In addition to under the short-circuit stress, the vertical GaN Fin-JFET was also found to exhibit a failure-toopen-circuit (FTO) signature under the through-fin avalanche (29). This FTO signature is desirable for system applications, at the same time, very interesting from the device physics standpoint, as in prior literature all Si and SiC power transistors were reported to show a failure-to-short-circuit (FTS) signature under the avalanche condition (29) with most of them showing a FTS signature under the short circuit condition (28). The detailed works on understanding the unique FTO signature of vertical GaN Fin-JFETs under the through-fin avalanche and short-circuit conditions are presented in ( 29) and (28), respectively.…”
Section: Failure-to-open-circuit Signaturementioning
confidence: 75%
“…In addition to under the short-circuit stress, the vertical GaN Fin-JFET was also found to exhibit a failure-toopen-circuit (FTO) signature under the through-fin avalanche (29). This FTO signature is desirable for system applications, at the same time, very interesting from the device physics standpoint, as in prior literature all Si and SiC power transistors were reported to show a failure-to-short-circuit (FTS) signature under the avalanche condition (29) with most of them showing a FTS signature under the short circuit condition (28). The detailed works on understanding the unique FTO signature of vertical GaN Fin-JFETs under the through-fin avalanche and short-circuit conditions are presented in ( 29) and (28), respectively.…”
Section: Failure-to-open-circuit Signaturementioning
confidence: 75%
“…The underlying device physics that enables a short-circuit capability at BV AVA is also found to be the 'avalanche through fin', as illustrated in Fig. 15(c) [166]. In this condition, the thermal (I AVA ) stress is mainly located at the fin channel, which is separated from the main blocking junction below the p-GaN gate that supports BV AVA .…”
Section: Emerging Vertical Gan Devicementioning
confidence: 86%
“…This approach enables a tSC over 3 µs in industrial Cascode GaN HEMTs. A more significant improvement is demonstrated in 600-700 V vertical GaN FETs, with a t SC over 30 µs at 400 V [147], [165], [166]. This vertical GaN FET will be elaborated in Section VII.…”
Section: A Short Circuit Robustnessmentioning
confidence: 94%
“…103) The capability of accommodating a high channel current also produces a good shortcircuit ruggedness of GaN Fin-JFETs at BV AVA . 28,105,106) The viability to accommodate two avalanche paths modulated by the gate driver is the inherent property of power JFETs and not a feature specific to GaN. By tuning the gate driver design (e.g.…”
Section: Key Device Design For Avalanche Breakdownmentioning
confidence: 99%