Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm

Liu, Mingshan; Scholz, Stefan; Hardtdegen, Alexander; Bae, Jin Hee; Hartmann, Jean‐Michel; Knoch, J.; Grützmacher, Detlev; Buca, D.; Zhao, Qing‐Tai

doi:10.1109/led.2020.2971034

Cited by 16 publications

(14 citation statements)

References 26 publications

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“…This effect stems from the increased gate control when the NW diameter is reduced. In fact, by representing the device as a series and parallel combination of capacitors in a top-of-the-barrier model, SS is approximately given by 𝑆𝑆 = 𝑘 𝐵 𝑇 𝑞 ln (10)…”

Section: Electrical Characterizationmentioning

confidence: 99%

“…6,8 Very recently, vertical Ge GAA NW pFETs with excellent subthreshold properties were reported. [10][11][12] However, vertical NW devices suffer from an inherently large contact resistance on top of nanowires due to the very small contact area, limiting the maximum achievable device performance. Technological approaches such as laser annealing, to increase the doping concentration, 13,14 or gate-last process to increase the top contact area, 15 have been investigated to reduce the contact resistivity.…”

Section: Introductionmentioning

confidence: 99%

“…All these lead to an increased carrier mobility by reducing the effective mass of carriers. Germanium with its high hole mobility and injection velocity has yielded superior p-MOSFETs electrical performance. , Very recently, vertical Ge GAA NW p-type FETs (p-FETs) with excellent subthreshold properties were reported. − However, vertical NW devices suffer from an inherently large contact resistance on top of NWs because of the very small contact area, limiting the maximum achievable device performance. Technological approaches such as laser annealing, to increase the doping concentration, , or gate-last process, to increase the top contact area, have been investigated to reduce the contact resistivity.…”

Section: Introductionmentioning

confidence: 99%

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Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance

Liu

Yang

Shkurmanov

et al. 2020

ACS Appl. Nano Mater.

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Harvesting the full potential of single crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high performance vertical gate-all-2 around nanowire p-type pFETs are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi-one-dimensional semiconductor nanowires fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW pFETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3×10 6 . A ~32% drive current enhancement is obtained compared to vertical Ge homojunction NW control devices. More interestingly, the drain-induced-barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor's key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.

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Section: Electrical Characterizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance

Liu

Yang

Shkurmanov

et al. 2020

ACS Appl. Nano Mater.

Self Cite

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“…[ 19 ] Germanium (Ge) in group IV, which has a narrow bandgap of ≈0.7 eV, is promising not only for Infrared (IR) detection but also for complementary metal‐oxide‐semiconductor (CMOS)‐compatible processes and designs. [ 20–23 ] In particular, a well‐established ion‐implantation process supported by an industry‐standard process simulation allows the design of more feasible vdW 2D/3D heterostructure photodiodes. [ 24 ] In such photodiode, the thickness and doping concentration of the 3D region can significantly affect the optical performance.…”

Section: Introductionmentioning

confidence: 99%

Design of p‐WSe₂/n‐Ge Heterojunctions for High‐Speed Broadband Photodetectors

Lee

Park

Youn

et al. 2021

Adv Funct Materials

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Van der Waals (vdW) 2D/3D heterostructures are extensively studied for high-performance photodetector applications. Until now, the type of 2D materials has been the primary area of interest rather than the design of 3D semiconductors. In this study, high-speed broadband photodiodes (PDs) based on vdW p-WSe 2 /n-Ge heterojunctions are reported, and the performance compared with different n-Ge regions formed via the ion-implantation process. The fabricated PD with a typical long n-Ge region and low doping concentration responds to a broad spectral range from visible to infrared near 1550 nm with a response time of ≈3 µs and responsivity of 1.3 A W −1 . The inferior responsivity of PDs with short n-Ge regions can be improved as demonstrated by experimental results and process simulation. Density functional theory calculations are performed to estimate the variation of the energy band structures with the doping concentration of n-Ge. Fast photoresponse and efficient carrier separation across the heterojunction can be expected regardless of the n-Ge doping concentration. Based on the experimental results together with theoretical band structure and process simulation, it is shown that the heterojunction with an optimized n-Ge design is a promising high-speed broadband photodetector that can be implemented with complementary metal-oxidesemiconductor design and fabrication processes.

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“…In order to reduce the footprint of a single CMOS device without degradation of performance, researchers have worked out a number of schemes. One key scheme is to increase the static control of gate by introducing FinFET [1], GAA nanowire [2] transistor and other potential structures. Among those, GAA nanowire transistor is regarded as a promising candidate of next generation CMOS device by many fabrication company due to its ultimate performance and compatibility with silicon fabrication process [3], [4].…”

Section: Introductionmentioning

confidence: 99%

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

2020

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In this letter, a novel Core-Substrate Gate-All-Around (CSGAA) nanowire structure has been proposed, investigated and simulated systematically based on 3D numerical simulation. This new structure is characterized by a Core-Substrate directly connected to the substrate wafer or well which is formed by a bulk region inside the tubular channel. Comparisons are carried out between conventional Gate-All-Around (GAA) nanowire transistor and newly proposed CSGAA structure. This budding structure exhibits a maximum of four orders of magnitude of reduction in off-state current, high saturation current and low performance degradation. With the help of Core-Substrate, the CSGAA structure is able to maintain excellent performance despite geometric and structural variation. Its special structure is very suitable for the use of vertical Gate-All-Around nanowire structure, making it a promising candidate of future high performance and low power CMOS devices. INDEX TERMS CMOS, core-substrate gate-all-around, CSGAA, field effect transistor, GAA, nanowire.

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Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm

Cited by 16 publications

References 26 publications

Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance

Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance

Design of p‐WSe₂/n‐Ge Heterojunctions for High‐Speed Broadband Photodetectors

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

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Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm

Cited by 16 publications

References 26 publications

Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance

Epitaxial GeSn/Ge Vertical Nanowires for p-Type Field-Effect Transistors with Enhanced Performance

Design of p‐WSe2/n‐Ge Heterojunctions for High‐Speed Broadband Photodetectors

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

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Design of p‐WSe₂/n‐Ge Heterojunctions for High‐Speed Broadband Photodetectors