Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration

Abstract

As Moore's law scaling approaches its physical limit, there is increased interest in memristors as a replacement to transistors in memory applications due to their smaller footprint and superior scaling characteristics. However, memristors are intrinsically two-terminal devices, requiring an underlying CMOS control interface for proper operation. Thus the integration of CMOS and memristors is essential to the development of memristor technology. Accordingly, hybrid configurations have been proposed that make use of the advantages of CMOS while utilizing a high density of memristors. However, memristor/CMOS hybrid fabrication is not trivial because high-density memories require memristor dimensions to be much smaller than those of the underlying CMOS. Additionally, memristors typically make use of materials not allowed in conventional CMOS fabrication. These issues point to a post-CMOS fabrication approach. An associated consideration for memristor/CMOS hybrid fabrication is the high cost of whole wafer fabrication. While whole wafer fabrication of memristors is viable for large volume markets, it is not a practical route for niche applications or research. While this suggests the use of CMOS dies, edge effects typically set the minimum processable die size, as in the case of edge beads, which limit the achievable resolution of devices. To address these issues, we present a hybrid integration approach for post-CMOS vertical integration of memristors that is independent of CMOS die size. Our approach enables the vertical integration of memristors with small foundry-fabricated dies using a waferscale integration scheme. We demonstrate this approach using a 2.2-mm × 3.2-mm CMOS die fabricated in a standard dualpoly, three-metal 0.5-µm technology process. We use solution-processed BCB as an adhesive to embed CMOS dies into silicon wafer handles, allowing for easy handling and compatibility with a variety of lithography techniques such as electron-beam, nanoimprint and photolithography. The process is compatible with spin-coated planarization layers, such as polyimide or BCB, if nanometer-scale roughness is desired. As a demonstration, vertically integrated Ag/SiO 2 /Pt switches were fabricated on CMOS using conventional photolithography techniques in a university cleanroom and tested through the CMOS circuitry. The measurements were compared to those of Ag/SiO 2 /Pt switches fabricated off-chip in a similar process and indicate that the memristor/CMOS hybrids were fully functional. We believe this hybrid approach will pave the way for hybrid CMOS-memristor chips, enabling applications from neuromorphic computing to high-density memories.

A 0.086-mm<formula> <tex>$^2$</tex> </formula> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

“…As the biological fan-in is on the order of 100 to 10,000 synapses per neuron, embedding locally an online learning rule such as spike-timing-dependent plasticity (STDP) [32] or spike-driven synaptic plasticity (SDSP) [33] in each single synapse is challenging [34]. Memristors promise new records, but high-yield co-integration with CMOS is still to be demonstrated [35], [36]. Second, the widespread leaky integrate-and-fire (LIF) neuron model has been shown to lack the essential behavior repertoire necessary to explore the computational properties of large neural networks [37].…”

Roadmap on emerging hardware and technology for machine learning

“…The resistance of these non-ideal interconnects increases as the size shrinks, causing a significant voltage drop across the array. This phenomenon will severely disturb the functionality of memristor crossbar arrays, resulting in insufficient power supply on individual devices and a large error rate during write/read operations [51]. Other problems include more device-to-device variation and current interference between more densely packed neighboring cells, known as the sneak path current problem [52].…”

Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence

“…Furthermore, a neuromorphic approach exploiting non-idealities instead of mitigating them could be particularly appropriate to alleviate the high levels of noise and mismatch encountered in these devices [86], or to leverage parasitic effects such as the conductance drift [90]. However, high-yield large-scale co-integration with CMOS is still at an early stage [91], [92].…”