Vertical Migration for Performance Enhancement in Layered Hardware/Firmware/Software Systems

Stockenberg, J. E.; Dam, A. van

doi:10.1109/c-m.1978.218182

Cited by 40 publications

(2 citation statements)

References 15 publications

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“…In many ways, our work is similar to the earlier work in writable microcode stores [ 1,20,24,29]--each technique dynamically augments the base instruction set with new application-specific instructions to improve application performance. The writable microcode approach creates new instructions by grouping together primitive datapath operations.…”

Section: Related Worksupporting

confidence: 48%

A high-performance microarchitecture with hardware-programmable functional units

Razdan¹,

Smith²

Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture

103

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This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC-a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.

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Section: Related Worksupporting

confidence: 48%

A high-performance microarchitecture with hardware-programmable functional units

Razdan¹,

Smith²

Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture

103

View full text Add to dashboard Cite

show abstract

“…OS design philosophy has also undergone a similar evolution, and explored designs for cross-layer optimization. Vertical Migration (VM) [46,45] aims to improve software performance by migrating application primitives into lower layers of the OS, thus, mitigating the overhead of inter-layer calls. In VM, an application function can be migrated to a lower layer if it is not using the abstractions provided by the higher layer.…”

Section: Related Workmentioning

confidence: 99%

An aspect-oriented approach to bypassing middleware layers

Demir

Dévanbu

Wohlstadter

et al. 2007

Proceedings of the 6th International Conference on Aspect-Oriented Software Development

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The layered architecture of middleware platforms (such as CORBA, SOAP, J2EE) is a mixed blessing. On the one hand, layers provide services such as demarshaling, session management, request despatching, quality-of-service (QoS) etc. In a typical middleware platform, every request passes through each layer, whether or not the services provided by that layer are needed for that specific request. This rigid layer processing can lower overall system throughput, and reduce availability and/or increase vulnerability to denial-of-service attacks. For use cases where the response is a simple function of the request input parameters, bypassing middleware layers may be permissible and highly advantageous. Unfortunately, if an application developer desires to selectively bypass the middleware, and process some requests in the lower layer, she has to write platform-specific, intricate low-level code. To evade this trap, we propose to extend the middleware platform with new aspect-oriented modeling syntax, code generation tools, and a development process for building bypassing implementations. Bypassing implementations provide better use of server's resources, leading to better overall client experience. Our core contribution is this idea: aspect-oriented extensions to IDL, additional code generation, along with an enhanced run-time, can enable application developers to conveniently bypass middleware layers when they are not needed, thus improving the server's performance and providing more "operational headroom".

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Operating system support for sharing writable control store

Winner¹,

Reed²

1984

Softw Pract Exp

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The design of a portable, production‐quality dynamic microprogramming system is given. The system is an extension to UNIX; it allows multiple users easily to time‐share the writable control store on a Perkin‐Elmer 3220. Each process may have its own microcode support, known as a microimage; processes may share microimages. Microimages are managed either in an optional software cache in kernel memory or in user memory where they are subject to secondary memory swapping. The physical loading of the WCS is accomplished in on‐demand fashion in the sense that only the first attempt to enter control store during a given scheduling quantum can cause a WCS fault. Users are prevented from erroneously entering control store by separate management of the control store entry points. The paper provides sufficient detail to allow other UNIX and similar systems to adopt this approach. Performance effects of WCS contention add from about 0.5 to 1 per cent overhead to the jobs, and the use of vertical migration has improved job run times up to 50 percent. This system has been in use for over a year and provides the main support for ongoing research into vertical migration.

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Vertical Migration for Performance Enhancement in Layered Hardware/Firmware/Software Systems

Cited by 40 publications

References 15 publications

A high-performance microarchitecture with hardware-programmable functional units

A high-performance microarchitecture with hardware-programmable functional units

An aspect-oriented approach to bypassing middleware layers

Operating system support for sharing writable control store

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