Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

Yang, Bing; Buddharaju, K.D.; Teo, S.H.G.; Singh, Navab; Lo, Guo‐Qiang; Kwong, Dim‐Lee

doi:10.1109/led.2008.2000617

Cited by 212 publications

(114 citation statements)

References 21 publications

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“…for chemical/biological sensing applications and their ability to be solution-processed and assembled from "semiconducting inks" using various alignment techniques, make them potential key building blocks for the manufacturing of chemical and biological sensors, [1][2][3] high performance field-effect transistors (FETs), [4][5][6] optical devices, 7,8 memory elements [9][10][11] and energy harvesting. 12,13 The availability of high quality semiconducting NWs in scalable quantities remains one of the main challenges for NW-based printed electronics.…”

mentioning

confidence: 99%

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

Constantinou¹,

Rigas

Castro

et al. 2016

ACS Nano

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Semiconducting nanowires (NWs) are becoming essential nano-building blocks for advanced devices from sensors to energy harvesters, however their full technology penetration requires large scale materials synthesis together with efficient NW assembly methods. We demonstrate a scalable one-step solution process for the direct selection, collection and ordered assembly of silicon NWs with desired electrical properties from a poly-disperse collection of NWs obtained from a Supercritical Fluid-Liquid-Solid growth process. Dielectrophoresis (DEP) combined with impedance spectroscopy provides a selection mechanism at high signal frequencies (>500 kHz) to isolate NWs with the highest conductivity and lowest defect density. The technique allows simultaneous control of five key parameters in NW assembly: selection of electrical properties, control of NW length, placement in pre-defined electrode areas, highly preferential orientation along the device channel and control of NWs deposition density from few to hundreds per device. Direct correlation between DEP signal frequency and deposited NWs conductivity is directly confirmed by field-effect transistor and conducting-AFM data. Fabricated NW transistor devices demonstrate excellent performance with up to 1.6 mA current, 106-107 on/off ratio and hole-mobility of 50 cm2 V-1 s-1

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confidence: 99%

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

Constantinou¹,

Rigas

Castro

et al. 2016

ACS Nano

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“…[1][2][3][4][5][6][7] The future may see the use of threedimensional (3D) MOSFETs, such as vertically stacked SiNW FETs, [8][9][10][11][12] for high device densities. An asymmetric channel structure is expected for the vertically stacked SiNW FETs because of the fabrication processes.…”

mentioning

confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

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“…Downscaling of channel length to 45 nm of MOSFET is restricting factor of static power consumption due to increase leakage in off state [9].In this paper performance analysis of GAA nanowire CMOS configuration is estimated and described [10]- [12]. High noise values in the subthreshold are the concerned factor that affects the normal behavior of switching and circuit performance of silicon nanowire FET.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Low Frequency Drain Current Model for Silicon Nanowire Gate-All-Around Field Effect Transistor

Sharma¹

2014

IJHIT

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Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

Cited by 212 publications

References 21 publications

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

Simultaneous Tunable Selection and Self-Assembly of Si Nanowires from Heterogeneous Feedstock

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Analysis of Low Frequency Drain Current Model for Silicon Nanowire Gate-All-Around Field Effect Transistor

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