2022
DOI: 10.1109/tpel.2021.3135386
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Vertical Stacked LEGO-PoL CPU Voltage Regulator

Abstract: This paper presents a 48 V-1 V merged-two-stage hybrid-switched-capacitor converter with a Linear Extendable Group Operated Point-of-Load (LEGO-PoL) architecture for ultra-high-current microprocessors, featuring 3-D stacked packaging and coupled inductors for miniaturized size, fast speed, and vertical power delivery. The architecture is highly modular and scalable. The switched-capacitor circuits are connected in series on the input side to split the high input voltage into multiple stacked voltage domains. T… Show more

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Cited by 78 publications
(26 citation statements)
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“…Compared to transformer-based topologies, SC converters utilize capacitors to undertake the major voltage stress for the large step-down ratio and can substantially reduce the converter size due to the superior capacitor energy storage density. By merging the two stages, one can soft charge the SC circuits to reduce the charge sharing loss [25]- [28], allowing the use of smaller capacitors or lower switching frequency. Single-stage architectures that have low component count and less power conversion stages can attain high efficiency and high power density, but they might experience difficulty realizing high control bandwidth.…”
Section: Socket Vrm Server Mother Boardmentioning
confidence: 99%
“…Compared to transformer-based topologies, SC converters utilize capacitors to undertake the major voltage stress for the large step-down ratio and can substantially reduce the converter size due to the superior capacitor energy storage density. By merging the two stages, one can soft charge the SC circuits to reduce the charge sharing loss [25]- [28], allowing the use of smaller capacitors or lower switching frequency. Single-stage architectures that have low component count and less power conversion stages can attain high efficiency and high power density, but they might experience difficulty realizing high control bandwidth.…”
Section: Socket Vrm Server Mother Boardmentioning
confidence: 99%
“…The equivalent circuit that was tested is shown in Fig. 4.4a and Fig. 4.4b shows V sec and V sw are observed against the control signals G and G ′ .…”
Section: Winding Lossmentioning
confidence: 99%
“…4.4a and Fig. 4.4b shows V sec and V sw are observed against the control signals G and G ′ . There is complementary switching performed between the clamp FET Q c and the primary-side main FET Q p1 .…”
Section: Winding Lossmentioning
confidence: 99%
“…Fig. 1b highlights a two-stage design, which is currently gaining popularity, wherein a direct 48 V to PoL conversion occurs [3]- [5]. Fig.…”
Section: Introductionmentioning
confidence: 99%