Vertically Integrated MOS Devices with Double Active Layers

Nishimura, Tsuyoshi; Sugahara, K.; Akasaka, Y.; Nakata, Hidetoshi

doi:10.7567/ssdm.1984.b-10-4

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1986

1991

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Cited by 3 publications

(2 citation statements)

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“…Thickness of the insulating layer has been carefully determined in order to avoid the degradation of the underlying device characteristics and also destructive damage due to heat diffusion from the upper layer while the laser recrystallization process was performed. Detailed studies have been reported elsewhere [5]. The resulting variation of the thickness was from 0.9 to 1.3 pm.…”

Section: Processmentioning

confidence: 99%

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SOI/SOI/Bulk-Si triple-level structure for three-dimensional devices

Sugahara

Nishimura

Kusunoki

et al. 1986

IEEE Electron Device Lett.

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The fabrication procedure of the SOI/SOI/bulk-Si triplelevel structure is developed by using the improved selective laser recrystallization technique and MOS LSI technology. The enlarged crystal stripes sandwiched by straight grain boundaries are produced on the planarized insulating film which overlies the device structure in bulkSi, and also SOUbulk-Si double-layered structure. The basic characteristics of MOSFET's in a triple-level structure are evaluated.

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Section: Processmentioning

confidence: 99%

“…In order to obtain single-crystalline silicon on a complicated device structure, we have improved the selective laser recrystallization technique [4] and fabricated the vertically integrated MOS devices with double-level active layers [ 5 ] .…”

Section: Introductionmentioning

confidence: 99%